JAJSGE8B March   2016  – October 2018 ADS1282-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements
    7. 7.7  Pulse-Sync Timing Requirements
    8. 7.8  Reset Timing Requirements
    9. 7.9  Read Data Timing Requirements
    10. 7.10 Switching Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Noise Performance
      2. 8.3.2  Input-Referred Noise
      3. 8.3.3  Idle Tones
      4. 8.3.4  Operating Mode
      5. 8.3.5  Analog Inputs and Multiplexer
      6. 8.3.6  PGA (Programmable Gain Amplifier)
      7. 8.3.7  ADC
      8. 8.3.8  Modulator
      9. 8.3.9  Modulator Over-Range
      10. 8.3.10 Modulator Input Impedance
      11. 8.3.11 Modulator Over-Range Detection (MFLAG)
      12. 8.3.12 Voltage Reference Inputs (VREFP, VREFN)
      13. 8.3.13 Digital Filter
        1. 8.3.13.1 Sinc Filter Stage (Sinx/X)
        2. 8.3.13.2 FIR Stage
        3. 8.3.13.3 Group Delay and Step Response
          1. 8.3.13.3.1 Linear Phase Response
          2. 8.3.13.3.2 Minimum Phase Response
        4. 8.3.13.4 HPF Stage
      14. 8.3.14 Master Clock Input (CLK)
      15. 8.3.15 Synchronization (SYNC Pin and Sync Command)
      16. 8.3.16 Pulse-Sync Mode
      17. 8.3.17 Continuous-Sync Mode
      18. 8.3.18 Reset (RESET Pin and Reset Command)
      19. 8.3.19 Power-Down (PWDN Pin and Standby Command)
      20. 8.3.20 Power-On Sequence
      21. 8.3.21 Serial Interface
        1. 8.3.21.1 Serial Clock (SCLK)
        2. 8.3.21.2 Data Input (DIN)
        3. 8.3.21.3 Data Output (DOUT)
        4. 8.3.21.4 Data Ready (DRDY)
      22. 8.3.22 Data Format
      23. 8.3.23 Reading Data
        1. 8.3.23.1 Read Data Continuous
        2. 8.3.23.2 Read Data by Command
      24. 8.3.24 One-Shot Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modulator Output Mode
    5. 8.5 Programming
      1. 8.5.1 Commands
        1. 8.5.1.1  WAKEUP: Wake-Up from Standby Mode
        2. 8.5.1.2  STANDBY: Standby Mode
        3. 8.5.1.3  SYNC: Synchronize the A/D Conversion
        4. 8.5.1.4  RESET: Reset the Device
        5. 8.5.1.5  RDATAC: Read Data Continuous
        6. 8.5.1.6  SDATAC: Stop Read Data Continuous
        7. 8.5.1.7  RDATA: Read Data By Command
        8. 8.5.1.8  RREG: Read Register Data
        9. 8.5.1.9  WREG: Write to Register
        10. 8.5.1.10 OFSCAL: Offset Calibration
        11. 8.5.1.11 GANCAL: Gain Calibration
      2. 8.5.2 Calibration Commands
        1. 8.5.2.1 OFSCAL Command
        2. 8.5.2.2 GANCAL Command
      3. 8.5.3 User Calibration
      4. 8.5.4 Configuration Guide
    6. 8.6 Register Maps
      1. 8.6.1 ADS1282-SP Register Map Information
      2. 8.6.2 ID Register
        1. Table 13. ID Register Field Descriptions
      3. 8.6.3 Configuration Registers
        1. 8.6.3.1 Configuration Register 0
          1. Table 14. Configuration Register 0 Field Descriptions
        2. 8.6.3.2 Configuration Register 1
          1. Table 15. Configuration Register 1 Field Descriptions
      4. 8.6.4 HPF1 and HPF0
        1. 8.6.4.1 High-Pass Filter Corner Frequency, Low Byte
        2. 8.6.4.2 High-Pass Filter Corner Frequency, High Byte
      5. 8.6.5 OFC2, OFC1, OFC0
        1. 8.6.5.1 Offset Calibration, Low Byte
        2. 8.6.5.2 Offset Calibration, Mid Byte
        3. 8.6.5.3 Offset Calibration, High Byte
      6. 8.6.6 FSC2, FSC1, FSC0
        1. 8.6.6.1 Full-Scale Calibration, Low Byte
        2. 8.6.6.2 Full-Scale Calibration, Mid Byte
        3. 8.6.6.3 Full-Scale Calibration, High Byte
      7. 8.6.7 Offset and Full-Scale Calibration Registers
        1. 8.6.7.1 OFC[2:0] Registers
        2. 8.6.7.2 FSC[2:0] Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Thermocouple Temperature Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Digital Connection to a Field Programmable Gate Array (FPGA) Device Typical Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 HPF伝達関数
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.17 Continuous-Sync Mode

In Continuous-sync mode, either a single sync pulse or a continuous clock may be applied. When a single sync pulse is applied (rising edge), the device behaves similar to the Pulse-sync mode. However, in this mode, DRDY continues to toggle unaffected but the DOUT output is held low until data are ready, 63 DRDY periods later. When the conversion data are non-zero, new conversion data are ready (as shown in Figure 46).

When a continuous clock is applied to the SYNC pin, the period must be an integral multiple of the output data rate or the device re-synchronizes. Synchronization results in the restarting of the digital filter and an interruption of 63 readings (refer to Pulse-Sync Timing Requirements).

When the sync input is first applied, the device re-synchronizes (under the condition tSYNC ≠ N / ƒDATA). DRDY continues to output but DOUT is held low until the new data are ready. Then, if SYNC is applied again and the period matches an integral multiple of the output data rate, the device freely runs without re-synchronization. The phase of the applied clock and output data rate (DRDY) are not matched because of the initial delay of DRDY after SYNC is first applied. Figure 47 shows the timing for Continuous-Sync mode.

A SYNC clock input should be applied after the Continuous-Sync mode is set. The first rising edge of SYNC then causes a synchronization.

ADS1282-SP ai_tim_pulse_bas418.gifFigure 46. Pulse-Sync Timing, Continuous-Sync Timing With Single Sync
ADS1282-SP ai_tim_contsync_bas418.gifFigure 47. Continuous-Sync Timing With Sync Clock