JAJSHV5B June 2017 – August 2019 ADS1287
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Collectively, the registers contain all the information needed to configure the device (such as data rate, filter mode, calibration, and so on). The registers are accessed by the read and write register commands (RREG and WREG, respectively). The registers are accessed either individually, or as a block by sending or receiving consecutive register data bytes. After the register write operation is completed, the conversion cycle restarts. Restart results in loss of the previous synchronization. Re-synchronize after writing the device registers; see the Synchronization section for details. Table 20 lists the ADS1287 registers.
ADDRESS | REGISTER | RESET VALUE | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|---|---|
00h | ID/CFG | X0h | ID[3:0] | MODE[2:1](1) | OFFSET | RESERVED | ||||
01h | CONFIG0 | 52h | SYNC | MODE[0](1) | DR[2:0] | PHASE | FILTR[1:0] | |||
02h | CONFIG1 | 08h | BIAS(2) | RESERVED | MUX[1:0] | CHOP | GAIN[2:0] | |||
03h | HPF0 | 32h | HPF[7:0] | |||||||
04h | HPF1 | 03h | HPF[15:8] | |||||||
05h | OFC0 | 00h | OFC[7:0] | |||||||
06h | OFC1 | 00h | OFC[15:8] | |||||||
07h | OFC2 | 00h | OFC[23:16] | |||||||
08h | FSC0 | 00h | FSC[7:0] | |||||||
09h | FSC1 | 00h | FSC[15:8] | |||||||
0Ah | FSC2 | 40h | FSC[23:16] |