JAJSIY6C December   2011  – April 2020 ADS1291 , ADS1292 , ADS1292R

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     ブロック概略図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EMI Filter
      2. 8.3.2  Input Multiplexer
        1. 8.3.2.1 Device Noise Measurements
        2. 8.3.2.2 Test Signals (TestP and TestN)
        3. 8.3.2.3 Auxiliary Differential Input (RESP_MODN/IN3N, RESP_MODN/IN3P)
        4. 8.3.2.4 Temperature Sensor (TEMPP, TEMPN)
        5. 8.3.2.5 Supply Measurements (MVDDP, MVDDN)
        6. 8.3.2.6 Lead-Off Excitation Signals (LoffP, LoffN)
        7. 8.3.2.7 Auxiliary Single-Ended Input
      3. 8.3.3  Analog Input
      4. 8.3.4  PGA Settings and Input Range
        1. 8.3.4.1 Input Common-Mode Range
        2. 8.3.4.2 Input Differential Dynamic Range
        3. 8.3.4.3 ADC ΔΣ Modulator
      5. 8.3.5  Digital Decimation Filter
        1. 8.3.5.1 Sinc Filter Stage (sinx / x)
      6. 8.3.6  Reference
      7. 8.3.7  Clock
      8. 8.3.8  Data Format
      9. 8.3.9  Multiple Device Configuration
        1. 8.3.9.1 Standard Mode
      10. 8.3.10 ECG-Specific Functions
        1. 8.3.10.1 Input Multiplexer (Rerouting the Right Leg Drive Signal)
          1. 8.3.10.1.1 Input Multiplexer (Measuring the Right Leg Drive Signal)
        2. 8.3.10.2 Lead-Off Detection
          1. 8.3.10.2.1 DC Lead-Off
          2. 8.3.10.2.2 AC Lead-Off
          3. 8.3.10.2.3 RLD Lead-Off
          4. 8.3.10.2.4 Right Leg Drive (RLD DC Bias Circuit)
            1. 8.3.10.2.4.1 RLD Configuration With Multiple Devices
        3. 8.3.10.3 PACE Detect
        4. 8.3.10.4 Respiration
          1. 8.3.10.4.1 Internal Respiration Circuitry With Internal Clock (ADS1292R)
          2. 8.3.10.4.2 Internal Respiration Circuitry With External Clock (ADS1292R)
      11. 8.3.11 Setting the Device for Basic Data Capture
        1. 8.3.11.1 Lead-Off
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Clock (SCLK)
        3. 8.5.1.3  Data Input (DIN)
        4. 8.5.1.4  Data Output (DOUT)
        5. 8.5.1.5  Data Retrieval
        6. 8.5.1.6  Data Ready (DRDY)
        7. 8.5.1.7  GPIO
        8. 8.5.1.8  Power-Down and Reset (PWDN/RESET)
        9. 8.5.1.9  START
        10. 8.5.1.10 Settling Time
        11. 8.5.1.11 Continuous Mode
        12. 8.5.1.12 Single-Shot Mode
      2. 8.5.2 SPI Command Definitions
        1. 8.5.2.1  WAKEUP: Exit STANDBY Mode
        2. 8.5.2.2  STANDBY: Enter STANDBY Mode
        3. 8.5.2.3  RESET: Reset Registers to Default Values
        4. 8.5.2.4  START: Start Conversions
        5. 8.5.2.5  STOP: Stop Conversions
        6. 8.5.2.6  OFFSETCAL: Channel Offset Calibration
        7. 8.5.2.7  RDATAC: Read Data Continuous
        8. 8.5.2.8  SDATAC: Stop Read Data Continuous
        9. 8.5.2.9  RDATA: Read Data
        10. 8.5.2.10 Sending Multi-Byte Commands
        11. 8.5.2.11 RREG: Read From Register
        12. 8.5.2.12 WREG: Write to Register
    6. 8.6 Register Maps
      1. 8.6.1 User Register Description
        1. 8.6.1.1  ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h)
          1. Table 17. ID: ID Control Register (Factory-Programmed, Read-Only) Field Descriptions
        2. 8.6.1.2  CONFIG1: Configuration Register 1 (address = 01h)
          1. Table 18. CONFIG1: Configuration Register 1 Field Descriptions
        3. 8.6.1.3  CONFIG2: Configuration Register 2 (address = 02h)
          1. Table 19. CONFIG2: Configuration Register 2 Field Descriptions
        4. 8.6.1.4  LOFF: Lead-Off Control Register (address = 03h)
          1. Table 20. LOFF: Lead-Off Control Register Field Descriptions
        5. 8.6.1.5  CH1SET: Channel 1 Settings (address = 04h)
          1. Table 21. CH1SET: Channel 1 Settings Field Descriptions
        6. 8.6.1.6  CH2SET: Channel 2 Settings (address = 05h)
          1. Table 22. CH2SET: Channel 2 Settings Field Descriptions
        7. 8.6.1.7  RLD_SENS: Right Leg Drive Sense Selection (address = 06h)
          1. Table 23. RLD_SENS: Right Leg Drive Sense Selection Field Descriptions
        8. 8.6.1.8  LOFF_SENS: Lead-Off Sense Selection (address = 07h)
          1. Table 24. LOFF_SENS: Lead-Off Sense Selection Field Descriptions
        9. 8.6.1.9  LOFF_STAT: Lead-Off Status (address = 08h)
          1. Table 25. LOFF_STAT: Lead-Off Status Field Descriptions
        10. 8.6.1.10 RESP1: Respiration Control Register 1 (address = 09h)
          1. Table 26. RESP1: Respiration Control Register 1 Field Descriptions
        11. 8.6.1.11 RESP2: Respiration Control Register 2 (address = 0Ah)
          1. Table 27. RESP2: Respiration Control Register 2 Field Descriptions
        12. 8.6.1.12 GPIO: General-Purpose I/O Register (address = 0Bh)
          1. Table 28. GPIO: General-Purpose I/O Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout
        1. 11.1.1.1 Power Supplies and Grounding
          1. 11.1.1.1.1 Connecting the Device to Unipolar (+3 V or +1.8 V) Supplies
          2. 11.1.1.1.2 Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies
        2. 11.1.1.2 Shielding Analog Signal Paths
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Noise Measurements

The ADS1291, ADS1292, and ADS1292R noise performance can be optimized by adjusting the data rate and PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the programmable gain amplifier (PGA) value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals. Table 1 through Table 8 summarize the ADS1291, ADS1292, and ADS1292R noise performance. The data are representative of typical noise performance at TA = +25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. For the shown data rates, the ratio is approximately 6.6.

Table 1 through Table 8 show measurements taken with an internal reference. The data are also representative of the ADS1291, ADS1292, and ADS1292R noise performance when using a low-noise external reference such as the REF5025.

In Table 1 through Table 8, µVRMS and µVPP are measured values. Effective resolution (EFF RESOL) and dynamic range (DYN RANGE) are calculated with Equation 1 and Equation 2.

Equation 1. ADS1291 ADS1292 ADS1292R eq_effres_sbas590.gif
Equation 2. ADS1291 ADS1292 ADS1292R eq_DR_sbas705.gif

Table 1. Input-Referred Noise (μVRMS / μVPP) 3-V Analog Supply and 2.42-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 1 PGA GAIN = 2
μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB
000 125 32.75 1.5 10.3 121.0 18.83 20.10 0.8 5.6 120.0 18.71 19.94
001 250 65.5 2.2 14.4 117.8 18.34 19.58 1.2 7.5 117.1 18.29 19.46
010 500 131 3.0 18.9 115.1 17.95 19.11 1.7 10.9 113.9 17.75 18.91
011 1000 262 4.6 30.8 111.3 17.25 18.49 2.5 15.6 110.6 17.23 18.37
100 2000 524 10.1 99 104.5 15.57 17.36 5.3 48 104.0 15.60 17.28
101 4000 1048 55.2 563 89.7 13.06 14.91 26.0 265 90.3 13.14 15.00
110 8000 2096 287.3 2930 75.4 10.68 12.53 144.1 1470 75.4 10.67 12.52
111 NA NA — — — — — — — — — —
(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 2. Input-Referred Noise (μVRMS / μVPP) 3-V Analog Supply and 2.42-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 3 PGA GAIN = 4
μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB
000 125 32.75 0.6 4.1 119.2 18.58 19.80 0.5 3.4 117.9 18.42 19.58
001 250 65.5 0.9 5.5 115.9 18.15 19.26 0.8 5.0 114.8 17.88 19.07
010 500 131 1.3 7.7 113.0 17.67 18.77 1.1 6.6 111.9 17.47 18.59
011 1000 262 1.9 12.0 109.5 17.02 18.19 1.6 10.3 108.7 16.83 18.06
100 2000 524 3.7 31 103.7 15.65 17.23 2.9 23 103.2 15.69 17.14
101 4000 1048 17.0 173 90.5 13.18 15.03 12.2 124 90.8 13.24 15.09
110 8000 2096 91.9 937 75.8 10.74 12.59 66.8 681 76.1 10.78 12.63
111 NA NA — — — — — — — — — —
(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 3. Input-Referred Noise (μVRMS / μVPP) 3-V Analog Supply and 2.42-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 6 PGA GAIN = 8
μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB
000 125 32.75 0.5 3.0 115.9 18.04 19.26 0.4 2.6 114.0 17.82 18.94
001 250 65.5 0.7 4.1 112.8 17.58 18.73 0.6 3.9 111.0 17.22 18.44
010 500 131 0.9 5.6 109.9 17.14 18.25 0.8 5.5 108.0 16.75 17.93
011 1000 262 1.3 8.7 106.8 16.49 17.73 1.2 7.6 104.9 16.26 17.42
100 2000 524 2.2 16 102.1 15.64 16.96 2.0 14 100.7 15.36 16.72
101 4000 1048 7.5 77 91.5 13.34 15.19 5.5 56 91.7 13.39 15.24
110 8000 2096 42.7 436 76.4 10.84 12.69 31.3 319 76.6 10.88 12.73
111 NA NA — — — — — — — — — —
(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 4. Input-Referred Noise (μVRMS / μVPP) 3-V Analog Supply and 2.42-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 12
μVRMS μVPP DYN RANGE EFF RESOL ENOB
000 125 32.75 0.4 2.5 111.3 17.31 18.48
001 250 65.5 0.5 3.5 108.4 16.81 18.01
010 500 131 0.8 5.0 105.0 16.29 17.44
011 1000 262 1.1 6.9 102.1 15.82 16.97
100 2000 524 1.7 11 98.6 15.21 16.38
101 4000 1048 3.5 36 92.0 13.44 15.29
110 8000 2096 20.1 205 76.9 10.93 12.78
111 NA NA — — — — —
(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 5. Input-Referred Noise (μVRMS / μVPP) 5-V Analog Supply and 4.033-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 1 PGA GAIN = 2
μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB
000 125 32.75 1.6 10.2 124.9 19.58 20.75 0.9 5.4 124.3 19.50 20.65
001 250 65.5 2.2 13.3 122.3 19.20 20.31 1.2 8.1 121.3 18.91 20.15
010 500 131 3.1 18.9 119.3 18.69 19.82 1.7 10.6 118.2 18.52 19.63
011 1000 262 4.9 31.9 115.2 17.94 19.14 2.7 17.9 114.4 17.77 19.00
100 2000 524 15.5 167 105.2 15.55 17.48 7.5 80 105.5 15.62 17.53
101 4000 1048 89.6 959 90.0 13.03 14.95 45.0 481 89.9 13.02 14.94
110 8000 2096 460.1 4923 75.8 10.67 12.59 229.0 2450 75.8 10.67 12.59
111 NA NA — — — — — — — — — —
(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 6. Input-Referred Noise (μVRMS / μVPP) 5-V Analog Supply and 4.033-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 3 PGA GAIN = 4
μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB
000 125 32.75 0.6 4.2 123.4 19.28 20.50 0.5 3.6 122.3 19.08 20.32
001 250 65.5 0.9 5.7 120.7 18.82 20.04 0.7 4.8 119.5 18.66 19.86
010 500 131 1.3 8.4 117.3 18.27 19.49 1.1 7.4 116.2 18.04 19.31
011 1000 262 2.0 13.3 113.5 17.62 18.85 1.6 11.0 112.7 17.48 18.72
100 2000 524 5.1 53 105.3 15.61 17.49 3.9 38 105.2 15.67 17.47
101 4000 1048 28.7 307 90.3 13.08 15.00 20.7 222 90.6 13.14 15.06
110 8000 2096 149.3 1598 76.0 10.70 12.62 111.8 1196 76.0 10.71 12.63
111 NA NA — — — — — — — — — —
(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 7. Input-Referred Noise (μVRMS / μVPP) 5-V Analog Supply and 4.033-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 6 PGA GAIN = 8
μVRMS μVPP DYN RANGE EFF RESOL ENOB μVRMS μVPP DYN RANGE EFF RESOL ENOB
000 125 32.75 0.5 3.0 120.4 18.78 19.99 0.4 2.7 118.5 18.48 19.68
001 250 65.5 0.6 4.0 117.5 18.36 19.52 0.6 3.8 115.7 18.01 19.21
010 500 131 0.9 6.0 114.3 17.75 18.99 0.8 5.3 112.8 17.53 18.74
011 1000 262 1.4 8.8 110.8 17.20 18.41 1.2 8.1 109.5 16.92 18.19
100 2000 524 2.8 24 104.6 15.74 17.38 2.3 18 103.6 15.73 17.22
101 4000 1048 13.3 142 91.0 13.20 15.12 9.3 100 91.5 13.29 15.21
110 8000 2096 71.5 765 76.4 10.77 12.69 52.3 560 76.6 10.80 12.72
111 NA NA — — — — — — — — — —
(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.

Table 8. Input-Referred Noise (μVRMS / μVPP) 5-V Analog Supply and 4.033-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA GAIN = 12
μVRMS μVPP DYN RANGE EFF RESOL ENOB
000 125 32.75 0.4 2.6 115.7 17.96 19.21
001 250 65.5 0.5 3.4 112.9 17.59 18.75
010 500 131 0.8 5.2 109.8 16.96 18.24
011 1000 262 1.1 6.9 106.6 16.56 17.70
100 2000 524 1.9 14 101.9 15.57 16.83
101 4000 1048 5.9 63 92.0 13.37 15.29
110 8000 2096 33.8 362 76.9 10.85 12.77
111 NA NA — — — — —
(1) At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.