The ADS1294, ADS1296, ADS1298 (ADS129x) and ADS1294R, ADS1296R ADS1298R (ADS129xR) are a family of multichannel, simultaneous sampling,
24-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with built-in programmable gain amplifiers (PGAs), internal reference, and an onboard oscillator. The ADS129x and ADS129xR incorporate all of the features that are commonly required in medical electrocardiogram (ECG) and electroencephalogram (EEG) applications. With high levels of integration and exceptional performance, the ADS129x and ADS129xR enables the development of scalable medical instrumentation systems at significantly reduced size, power, and overall cost.
The ADS129x and ADS129xR have a flexible input multiplexer (mux) per channel that can be independently connected to the internally-generated signals for test, temperature, and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the right leg drive (RLD) output signal. The ADS129x and ADS129xR operate at data rates as high as 32 kSPS, thereby allowing the implementation of software pace detection. Lead-off detection can be implemented internal to the device, either with a pullup or pulldown resistor, or an excitation current sink or source. Three integrated amplifiers generate the Wilson central terminal (WCT) and the Goldberger central terminals (GCT) required for a standard 12-lead ECG. The ADS129xR versions include a fully integrated, respiration impedance measurement function. Multiple ADS129x and ADS129xR devices can be cascaded in high channel count systems in a daisy-chain configuration.
Package options include a tiny 8-mm × 8-mm,
64-ball BGA, and a TQFP-64. The ADS129x BGA version is specified over the commercial temperature range of 0°C to 70°C. The ADS129xR BGA and ADS129x TQFP versions are specified over the industrial temperature range of –40°C to +85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS129x, ADS129xR | NFBGA (64) | 8.00 mm × 8.00 mm |
TQFP (64) | 10.00 mm × 10.00 mm |
Changes from J Revision (January 2014) to K Revision
Changes from I Revision (January 2012) to J Revision
Changes from H Revision (October 2011) to I Revision
Changes from G Revision (February 2011) to H Revision
Changes from F Revision (October 2010) to G Revision
PRODUCT | PACKAGE OPTIONS | OPERATING TEMPERATURE RANGE | RESPIRATION CIRCUITRY | CHANNELS | ADC RESOLUTION | MAXIMUM SAMPLING RATE |
---|---|---|---|---|---|---|
ADS1194 | TQFP-64 | 0°C to 70°C | No | 4 | 16 | 8 kSPS |
NFBGA-64 | 0°C to 70°C | |||||
ADS1196 | TQFP-64 | 0°C to 70°C | No | 6 | 16 | 8 kSPS |
NFBGA-64 | 0°C to 70°C | |||||
ADS1198 | TQFP-64 | 0°C to 70°C | No | 8 | 16 | 8 kSPS |
NFBGA-64 | 0°C to 70°C | |||||
ADS1294 | TQFP-64 | –40°C to +85°C | External | 4 | 24 | 32 kSPS |
NFBGA-64 | 0°C to 70°C | |||||
ADS1294R | NFBGA-64 | –40°C to +85°C | Yes | |||
ADS1296 | TQFP-64 | –40°C to +85°C | External | 6 | 24 | 32 kSPS |
NFBGA-64 | 0°C to 70°C | |||||
ADS1296R | NFBGA-64 | –40°C to +85°C | Yes | |||
ADS1298 | TQFP-64 | –40°C to +85°C | External | 8 | 24 | 32 kSPS |
NFBGA-64 | 0°C to 70°C | |||||
ADS1298R | NFBGA-64 | –40°C to +85°C | Yes |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1A | IN8P(1) | Analog input | Differential analog positive input 8 (ADS1298 and ADS1298R) |
1B | IN7P(1) | Analog input | Differential analog positive input 7 (ADS1298 and ADS1298R) |
1C | IN6P(1) | Analog input | Differential analog positive input 6 (ADS1296, ADS1298, ADS1296R, ADS1298R) |
1D | IN5P(1) | Analog input | Differential analog positive input 5 (ADS1296, ADS1298, ADS1296R, ADS1298R) |
1E | IN4P(1) | Analog input | Differential analog positive input 4 |
1F | IN3P(1) | Analog input | Differential analog positive input 3 |
1G | IN2P(1) | Analog input | Differential analog positive input 2 |
1H | IN1P(1) | Analog input | Differential analog positive input 1 |
2A | IN8N(1) | Analog input | Differential analog negative input 8 (ADS1298, ADS1298R) |
2B | IN7N(1) | Analog input | Differential analog negative input (ADS1298, ADS1298R) |
2C | IN6N(1) | Analog input | Differential analog negative input 6 (ADS1296, ADS1298, ADS1296R, ADS1298R) |
2D | IN5N(1) | Analog input | Differential analog negative input 5 (ADS1296, ADS1298, ADS1296R, ADS1298R) |
2E | IN4N(1) | Analog input | Differential analog negative input 4 |
2F | IN3N(1) | Analog input | Differential analog negative input 3 |
2G | IN2N(1) | Analog input | Differential analog negative input 2 |
2H | IN1N(1) | Analog input | Differential analog negative input 1 |
3A | RLDIN(1) | Analog input | Right leg drive input to mux |
3B | RLDOUT | Analog output | Right leg drive output |
3C | RLDINV | Analog input/output | Right leg drive inverting input |
3D | WCT | Analog output | Wilson central terminal output |
3E | TESTP_PACE_OUT1(1) | Analog input/buffer output | Internal test signal or single-ended buffer output based on register settings |
3F | TESTN_PACE_OUT2(1) | Analog input/output | Internal test signal or single-ended buffer output based on register settings |
3G | VCAP4 | — | Analog bypass capacitor; connect 1-μF capacitor to AVSS |
3H | VREFP | Analog input/output | Positive reference input/output voltage |
4A | AVDD | Supply | Analog supply |
4B | AVDD | Supply | Analog supply |
4C | RLDREF | Analog input | Right leg drive noninverting input |
4D | AVSS | Supply | Analog ground |
4E | RESV1 | Digital input | Reserved for future use; must tie to logic low (DGND). |
4F | RESP_MODN | Analog output | ADS129xR: modulation clock for respiration measurement, negative side. ADS129x: leave floating. |
4G | RESP_MODP | Analog output | ADS129xR: modulation clock for respiration measurement, positive side. ADS129x: leave floating. |
4H | VREFN | Analog input | Negative reference voltage |
5A | AVSS | Supply | Analog ground |
5B | AVSS | Supply | Analog ground |
5C | AVSS | Supply | Analog ground |
5D | AVSS | Supply | Analog ground |
5E | GPIO4 | Digital input/output | General-purpose input/output pin 4 |
5F | GPIO1 | Digital input/output | General-purpose input/output pin 1 |
5G | PWDN | Digital input | Power-down pin; active low |
5H | VCAP1 | — | Analog bypass capacitor; connect 22-μF capacitor to AVSS |
6A | AVDD | Supply | Analog supply |
6B | AVDD | Supply | Analog supply |
6C | AVDD | Supply | Analog supply |
6D | DRDY | Digital output | Data ready; active low |
6E | GPIO3 | Digital input/output | General purpose input/output pin 3 |
6F | DAISY_IN(2) | Digital input | Daisy-chain input; if not used, short to DGND. |
6G | RESET | Digital input | System-reset pin; active low |
6H | VCAP2 | — | Analog bypass capacitor; connect 1-μF capacitor to AVSS |
7A | AVDD1 | Supply | Analog supply for charge pump |
7B | VCAP3 | — | Analog bypass capacitor; internally generated AVDD + 1.9 V; connect 1-μF capacitor to AVSS |
7C | DGND | Supply | Digital ground |
7D | DGND | Supply | Digital ground |
7E | GPIO2 | Digital input/output | General-purpose input/output pin 2 |
7F | CS | Digital input | SPI chip select; active low |
7G | START | Digital input | Start conversion |
7H | DGND | Supply | Digital ground |
8A | AVSS1 | Supply | Analog ground for charge pump |
8B | CLKSEL | Digital input | Master clock select |
8C | DVDD | Supply | Digital power supply |
8D | DVDD | Supply | Digital power supply |
8E | DOUT | Digital output | SPI data output |
8F | SCLK | Digital input | SPI clock |
8G | CLK | Digital input/output | External Master clock input or internal clock output. |
8H | DIN | Digital input | SPI data input |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | IN8N(1) | Analog input | Differential analog negative input 8 (ADS1298) |
2 | IN8P(1) | Analog input | Differential analog positive input 8 (ADS1298) |
3 | IN7N(1) | Analog input | Differential analog negative input 7 (ADS1298) |
4 | IN7P(1) | Analog input | Differential analog positive input 7 (ADS1298) |
5 | IN6N(1) | Analog input | Differential analog negative input 6 (ADS1296, ADS1298) |
6 | IN6P(1) | Analog input | Differential analog positive input 6 (ADS1296, ADS1298) |
7 | IN5N(1) | Analog input | Differential analog negative input 5 (ADS1296, ADS1298) |
8 | IN5P(1) | Analog input | Differential analog positive input 5 (ADS1296, ADS1298) |
9 | IN4N(1) | Analog input | Differential analog negative input 4 |
10 | IN4P(1) | Analog input | Differential analog positive input 4 |
11 | IN3N(1) | Analog input | Differential analog negative input 3 |
12 | IN3P(1) | Analog input | Differential analog positive input 3 |
13 | IN2N(1) | Analog input | Differential analog negative input 2 |
14 | IN2P(1) | Analog input | Differential analog positive input 2 |
15 | IN1N(1) | Analog input | Differential analog negative input 1 |
16 | IN1P(1) | Analog input | Differential analog positive input 1 |
17 | TESTP_PACE_OUT1(1) | Analog input/buffer output | Internal test signal/single-ended buffer output based on register settings |
18 | TESTN_PACE_OUT2(1) | Analog input/output | Internal test signal/single-ended buffer output based on register settings |
19 | AVDD | Supply | Analog supply |
20 | AVSS | Supply | Analog ground |
21 | AVDD | Supply | Analog supply |
22 | AVDD | Supply | Analog supply |
23 | AVSS | Supply | Analog ground |
24 | VREFP | Analog input/output | Positive reference input/output voltage |
25 | VREFN | Analog input | Negative reference voltage |
26 | VCAP4 | — | Analog bypass capacitor; connect 1-μF capacitor to AVSS |
27 | NC | — | No connection, can be connected to AVDD or AVSS with a 10-kΩ resistor |
28 | VCAP1 | — | Analog bypass capacitor; connect 22-μF capacitor to AVSS |
29 | NC | — | No connection, can be connected to AVDD or AVSS with a 10-kΩ resistor |
30 | VCAP2 | — | Analog bypass capacitor; connect 1-μF capacitor to AVSS |
31 | RESV1 | Digital input | Reserved for future use; must tie to logic low (DGND). |
32 | AVSS | Supply | Analog ground |
33 | DGND | Supply | Digital ground |
34 | DIN | Digital input | SPI data input |
35 | PWDN | Digital input | Power-down pin; active low |
36 | RESET | Digital input | System-reset pin; active low |
37 | CLK | Digital input/output | External Master clock input or internal clock output. |
38 | START | Digital input | Start conversion |
39 | CS | Digital input | SPI chip select; active low |
40 | SCLK | Digital input | SPI clock |
41 | DAISY_IN(2) | Digital input | Daisy-chain input; if not used, short to DGND. |
42 | GPIO1 | Digital input/output | General-purpose input/output pin 1 |
43 | DOUT | Digital output | SPI data output |
44 | GPIO2 | Digital input/output | General-purpose input/output pin 2 |
45 | GPIO3 | Digital input/output | General-purpose input/output pin 3 |
46 | GPIO4 | Digital input/output | General-purpose input/output pin 4 |
47 | DRDY | Digital output | Data ready; active low |
48 | DVDD | Supply | Digital power supply |
49 | DGND | Supply | Digital ground |
50 | DVDD | Supply | Digital power supply |
51 | DGND | Supply | Digital ground |
52 | CLKSEL | Digital input | Master clock select |
53 | AVSS1 | Supply | Analog ground |
54 | AVDD1 | Supply | Analog supply |
55 | VCAP3 | — | Analog bypass capacitor; internally generated AVDD + 1.9 V; connect 1-μF capacitor to AVSS |
56 | AVDD | Supply | Analog supply |
57 | AVSS | Supply | Analog ground |
58 | AVSS | Supply | Analog ground |
59 | AVDD | Supply | Analog supply |
60 | RLDREF | Analog input | Right leg drive noninverting input |
61 | RLDINV | Analog input/output | Right leg drive inverting input |
62 | RLDIN(1) | Analog input | Right leg drive input to mux |
63 | RLDOUT | Analog output | Right leg drive output |
64 | WCT | Analog output | Wilson Central Terminal output |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
POWER SUPPLY | |||||
Analog power supply (AVDD – AVSS) | 2.7 | 3 | 5.25 | V | |
Digital power supply (DVDD) | 1.65 | 1.8 | 3.6 | V | |
AVDD – DVDD | –2.1 | 3.6 | V | ||
ANALOG INPUTS | |||||
Full-scale differential input voltage range (AINP – AINN) | ±VREF / Gain | V | |||
Common-mode input voltage | See the Input Common-Mode Range subsection of the PGA Settings and Input Range section | ||||
VOLTAGE REFERENCE INPUTS | |||||
Differential reference voltage | 3-V supply VREF = (VREFP – VREFN) | 2.5 | V | ||
5-V supply VREF = (VREFP – VREFN) | 4 | V | |||
Negative input (VREFN) | AVSS | V | |||
Positive input (VREFP) | AVSS + 2.5 | V | |||
CLOCK INPUT | |||||
External clock input frequency | CLKSEL pin = 0 | 1.94 | 2.048 | 2.25 | MHz |
DIGITAL INPUTS | |||||
Input Voltage | DGND | DVDD | V | ||
TEMPERATURE RANGE | |||||
Operating temperature range | Commercial grade | 0 | 70 | °C | |
Industrial grade | –40 | 85 | °C |
THERMAL METRIC(1) | ADS129x, ADS129xR | UNIT | ||
---|---|---|---|---|
PAG (TQFP) | ZXG (NFBGA) | |||
64 PINS | 64 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 35 | 48 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 31 | 8 | °C/W |
RθJB | Junction-to-board thermal resistance | 26 | 25 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | N/A | 22 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ANALOG INPUTS | ||||||||
Input capacitance | 20 | pF | ||||||
Input bias current | TA = 25°C, input = 1.5 V | ±200 | pA | |||||
TA = 0°C to 70°C, input = 1.5 V | ±1 | nA | ||||||
TA = –40°C to +85°C, input = 1.5 V | ±1.2 | nA | ||||||
DC input impedance | No lead-off | 1000 | MΩ | |||||
Current source lead-off detection | 500 | MΩ | ||||||
Pullup resistor lead-off detection | 10 | MΩ | ||||||
PGA PERFORMANCE | ||||||||
Gain settings | 1, 2, 3, 4, 6, 8, 12 | |||||||
Bandwidth | See Table 5 | |||||||
ADC PERFORMANCE | ||||||||
Resolution | Data rates up to 8 kSPS, no missing codes | 24 | Bits | |||||
16-kSPS data rate | 19 | Bits | ||||||
32-kSPS data rate | 17 | Bits | ||||||
Data rate | fCLK = 2.048 MHz, HR mode | 500 | 32000 | SPS | ||||
fCLK = 2.048 MHz, LP mode | 250 | 16000 | SPS | |||||
DC CHANNEL PERFORMANCE | ||||||||
Input-referred noise | Gain = 6(1), 10 seconds of data | 5 | μVPP | |||||
Gain = 6, 256 points, 0.5 seconds of data | 4 | 7 | μVPP | |||||
Gain settings ≠ 6, data rates≠ 500 SPS | See Noise Measurements section | |||||||
Integral nonlinearity(5) | Full-scale with gain = 6, best fit | 8 | ppm | |||||
Full-scale with gain = 6, best fit, ADS129xR channel 1 |
40 | ppm | ||||||
–20 dBFS with gain = 6, best fit, ADS129xR channel 1 |
8 | ppm | ||||||
Offset error | ±500 | µV | ||||||
Offset error drift | 2 | µV/°C | ||||||
Gain error | Excluding voltage reference error | ±0.2 | ±0.5 | % of FS | ||||
Gain drift | Excluding voltage reference drift | 5 | ppm/°C | |||||
Gain match between channels | 0.3 | % of FS | ||||||
AC CHANNEL PERFORMANCE | ||||||||
CMRR | Common-mode rejection ratio | fCM = 50 Hz, 60 Hz(2) | –105 | –115 | dB | |||
PSRR | Power-supply rejection ratio | fPS = 50 Hz, 60 Hz | 90 | dB | ||||
Crosstalk | fIN = 50 Hz, 60 Hz | –126 | dB | |||||
SNR | Signal-to-noise ratio | fIN = 10 Hz input, gain = 6 | 112 | dB | ||||
THD | Total harmonic distortion(5) | 10 Hz, –0.5 dBFs | –98 | dB | ||||
ADS129xR channel 1, 10 Hz, –0.5 dBFs | –70 | dB | ||||||
100 Hz, –0.5 dBFs(4) | –100 | dB | ||||||
ADS129xR channel 1, 100 Hz, –0.5 dBFs(4) | –68 | dB | ||||||
ADS129xR channel 1, 100 Hz, –20 dBFs(4) | –86 | dB | ||||||
DIGITAL FILTER | ||||||||
–3-dB bandwidth | 0.262 fDR | Hz | ||||||
Digital filter settling | Full setting | 4 | Conversions | |||||
RIGHT LEG DRIVE (RLD) AMPLIFIER AND PACE AMPLIFIERS | ||||||||
RLD integrated noise | BW = 150 Hz | 7 | μVRMS | |||||
Pace integrated noise | BW = 8 kHz | 20 | µVRMS | |||||
Pace-amplifier crosstalk | Crosstalk between pace amplifiers | 60 | dB | |||||
Gain bandwidth product | 50 kΩ || 10 pF load, gain = 1 | 100 | kHz | |||||
Slew rate | 50 kΩ || 10 pF load, gain = 1 | 0.25 | V/μs | |||||
Pace and RLD amplifier drive strength | Short circuit to GND (AVDD = 3 V) | 270 | μA | |||||
Short circuit to supply (AVDD = 3 V) | 550 | μA | ||||||
Short circuit to GND (AVDD = 5 V) | 490 | μA | ||||||
Short circuit to supply (AVDD = 5 V) | 810 | μA | ||||||
Pace and RLD current | Peak swing (AVSS + 0.3 V to AVDD + 0.3 V) at AVDD = 3 V |
50 | μA | |||||
Peak swing (AVSS + 0.3 V to AVDD + 0.3 V) at AVDD = 5 V |
75 | μA | ||||||
Pace-amplifier output resistance | 100 | Ω | ||||||
Total harmonic distortion | fIN = 100 Hz, gain = 1 | –70 | dB | |||||
Common-mode input range | AVSS + 0.7 | AVDD – 0.3 | V | |||||
Common-mode resistor matching | Internal 200-kΩ resistor matching | 0.1% | ||||||
Short-circuit current | ±0.25 | mA | ||||||
Quiescent power consumption | Either RLD or pace amplifier | 20 | μA | |||||
WILSON CENTRAL TERMINAL (WCT) AMPLIFIER | ||||||||
Integrated noise | BW = 150 Hz | See Table 6 | nV/√Hz | |||||
Gain bandwidth product | See Table 6 | kHz | ||||||
Slew rate | See Table 6 | V/s | ||||||
Total harmonic distortion | fIN = 100 Hz | 90 | dB | |||||
Common-mode input range | AVSS + 0.3 | AVDD – 0.3 | V | |||||
Short-circuit current | Through internal 30-kΩ resistor | ±0.25 | mA | |||||
Quiescent power consumption | See Table 6 | μA | ||||||
LEAD-OFF DETECT | ||||||||
Frequency | See Table 16 for settings | 0, fDR/4 | kHz | |||||
Current | See Table 16 for settings | 6, 12, 18, 24 | nA | |||||
Current accuracy | ±20% | |||||||
Comparator threshold accuracy | ±30 | mV | ||||||
RESPIRATION (ADS129xR ONLY) | ||||||||
Frequency | Internal source | 32, 64 | kHz | |||||
External source | 32 | 64 | kHz | |||||
Phase shift | See Table 16 for settings | 22.5 | 90 | 157.5 | Degrees | |||
Impedance range | IRESP = 30 μA | 10 | kΩ | |||||
Impedance measurement noise | 0.05-Hz to 2-Hz brick wall filter, 32-kHz modulation clock, phase = 112.5, IRESP = 30 μA with 2-kΩ baseline load, gain = 4 | 20 | mΩPP | |||||
Modulator current | internal reference, signal path = 82 kΩ, baseline = 2.21 kΩ |
29 | µA | |||||
EXTERNAL REFERENCE | ||||||||
Input impedance | 10 | kΩ | ||||||
INTERNAL REFERENCE | ||||||||
Output voltage | Register bit CONFIG3.VREF_4V = 0, AVDD ≥ 2.7 V |
2.4 | V | |||||
Register bit CONFIG3.VREF_4V = 1, AVDD ≥ 4.4 V |
4 | V | ||||||
VREF accuracy | ±0.2% | |||||||
Internal reference drift | TA = 25°C | 35 | ppm/°C | |||||
Commercial grade, 0°C to 70°C | 35 | ppm | ||||||
Industrial grade, –40°C to 85°C | 45 | ppm | ||||||
Start-up time | 150 | ms | ||||||
SYSTEM MONITORS | ||||||||
Analog-supply reading error | 2% | |||||||
Digital-supply reading error | 2% | |||||||
Device wakeup | From power up to DRDY low | 150 | ms | |||||
STANDBY mode | 9 | ms | ||||||
Temperature-sensor reading, voltage | TA = 25°C | 145 | mV | |||||
Temperature-sensor reading, coefficient | 490 | μV/°C | ||||||
Test-signal frequency | See Table 16 for settings | fCLK / 221, fCLK / 220 | Hz | |||||
Test-signal voltage | See Table 16 for settings | ±1, ±2 | mV | |||||
Test-signal accuracy | ±2% | |||||||
CLOCK | ||||||||
Internal-oscillator clock frequency | Nominal frequency | 2.048 | MHz | |||||
Internal clock accuracy | TA = 25°C | ±0.5% | ||||||
0°C ≤ TA ≤ 70°C | ±2% | |||||||
–40°C ≤ TA ≤ 85°C, industrial grade versions only | ±2.5% | |||||||
Internal-oscillator start-up time | 20 | μs | ||||||
Internal-oscillator power consumption | 120 | μW | ||||||
DIGITAL INPUT/OUTPUT (DVDD = 1.65 V to 3.6 V) | ||||||||
VIH | High-level inpout voltage | 0.8 DVDD | DVDD + 0.1 | V | ||||
VIL | Low-level input voltage | –0.1 | 0.2 DVDD | V | ||||
VOH | High-level output voltage | IOH = –500 μA | DVDD – 0.4 | V | ||||
VOL | Low-level output voltage | IOL = 500 μA | 0.4 | V | ||||
IIN | Input current | 0 V < VDigitalInput < DVDD | –10 | 10 | μA | |||
POWER SUPPLY (RLD, WCT, AND PACE AMPLIFIERS TURNED OFF) | ||||||||
IAVDD | AVDD current | AVDD – AVSS = 3 V | HR mode (ADS1298) | 2.75 | mA | |||
LP mode(6) (ADS1298) | 1.8 | mA | ||||||
AVDD – AVSS = 5 V | HR mode (ADS1298) | 3.1 | mA | |||||
LP mode (ADS1298) | 2.1 | mA | ||||||
IDVDD | DVDD current | DVDD = 1.8 V | HR mode (ADS1298) | 0.3 | mA | |||
LP mode (ADS1298) | 0.3 | mA | ||||||
DVDD = 3 V | HR mode (ADS1298) | 0.5 | mA | |||||
LP mode (ADS1298) | 0.5 | mA | ||||||
Power dissipation | ADS1298, ADS1298R, AVDD – AVSS = 3 V | HR mode | 8.8 | 9.5 | mW | |||
LP mode (250 SPS) | 6.0 | 7.0 | mW | |||||
ADS1296, ADS1296R, AVDD – AVSS = 3 V | HR mode | 7.2 | 7.9 | mW | ||||
LP mode (250 SPS) | 5.3 | 6.6 | mW | |||||
ADS1294, ADS1294R, AVDD – AVSS = 3 V | HR mode | 5.4 | 6 | mW | ||||
LP mode (250 SPS) | 4.1 | 4.4 | mW | |||||
ADS1298, ADS1298R, AVDD – AVSS = 5 V | HR mode | 17.5 | mW | |||||
LP mode (250 SPS) | 12.5 | mW | ||||||
ADS1296, ADS1296R, AVDD – AVSS = 5 V | HR mode | 14.1 | mW | |||||
LP mode (250 SPS) | 10 | mW | ||||||
ADS1294, ADS1294R, AVDD – AVSS = 5 V | HR mode | 10.1 | mW | |||||
LP mode (250 SPS) | 8.3 | mW | ||||||
Power-down | AVDD – AVSS = 3 V | 10 | μW | |||||
AVDD – AVSS = 5 V | 20 | μW | ||||||
Standby mode | AVDD – AVSS = 3 V | 2 | mW | |||||
AVDD – AVSS = 5 V | 4 | mW | ||||||
Quiescent channel power | AVDD – AVSS = 3 V, PGA + ADC | 818 | μW | |||||
AVDD – AVSS = 5 V, PGA + ADC | 1.5 | mW |
2.7 V ≤ DVDD ≤ 3.6 V | 1.65 V ≤ DVDD ≤ 2 V | UNIT | ||||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
tCLK | Master clock period | 414 | 514 | 414 | 514 | ns |
tCSSC | CS low to first SCLK, setup time | 6 | 17 | ns | ||
tSCLK | SCLK period | 50 | 66.6 | ns | ||
tSPWH, L | SCLK pulse width, high and low | 15 | 25 | ns | ||
tDIST | DIN valid to SCLK falling edge: setup time | 10 | 10 | ns | ||
tDIHD | Valid DIN after SCLK falling edge: hold time | 10 | 11 | ns | ||
tCSH | CS high pulse | 2 | 2 | tCLK | ||
tSCCS | Eighth SCLK falling edge to CS high | 4 | 4 | tCLK | ||
tSDECODE | Command decode time | 4 | 4 | tCLK | ||
tDISCK2ST | DAISY_IN valid to SCLK rising edge: setup time | 10 | 10 | ns | ||
tDISCK2HT | DAISY_IN valid after SCLK rising edge: hold time | 10 | 10 | ns |
PARAMETER | 2.7 V ≤ DVDD ≤ 3.6 V | 1.65 V ≤ DVDD ≤ 2 V | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
tDOHD | SCLK falling edge to invalid DOUT: hold time | 10 | 10 | ns | ||
tDOPD | SCLK rising edge to DOUT valid: setup time | 17 | 32 | ns | ||
tCSDOD | CS low to DOUT driven | 10 | 20 | ns | ||
tCSDOZ | CS high to DOUT Hi-Z | 10 | 20 | ns |