SBAS459K January   2010  – August 2015 ADS1294 , ADS1294R , ADS1296 , ADS1296R , ADS1298 , ADS1298R

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Functionality
        1. 9.3.1.1 EMI Filter
        2. 9.3.1.2 Analog Input Structure
        3. 9.3.1.3 Input Multiplexer
          1. 9.3.1.3.1 Device Noise Measurements
          2. 9.3.1.3.2 Test Signals (TestP and TestN)
          3. 9.3.1.3.3 Auxiliary Differential Input (TESTP_PACE_OUT1, TESTN_PACE_OUT2)
          4. 9.3.1.3.4 Temperature Sensor (TempP, TempN)
          5. 9.3.1.3.5 Supply Measurements (MVDDP, MVDDN)
          6. 9.3.1.3.6 Lead-Off Excitation Signals (LoffP, LoffN)
          7. 9.3.1.3.7 Auxiliary Single-Ended Input
        4. 9.3.1.4 Analog Input
        5. 9.3.1.5 PGA Settings and Input Range
          1. 9.3.1.5.1 Input Common-Mode Range
          2. 9.3.1.5.2 Input Differential Dynamic Range
          3. 9.3.1.5.3 ADC Delta-Sigma Modulator
        6. 9.3.1.6 Reference
        7. 9.3.1.7 ECG-Specific Functions
          1. 9.3.1.7.1 Input Multiplexer (Rerouting The Right Leg Drive Signal)
          2. 9.3.1.7.2 Input Multiplexer (Measuring The Right Leg Drive Signal)
          3. 9.3.1.7.3 Wilson Central Terminal (WCT) and Chest Leads
            1. 9.3.1.7.3.1 Augmented Leads
            2. 9.3.1.7.3.2 Right Leg Drive with the WCT Point
          4. 9.3.1.7.4 Lead-Off Detection
            1. 9.3.1.7.4.1 DC Lead-Off
            2. 9.3.1.7.4.2 AC Lead-Off
          5. 9.3.1.7.5 RLD Lead-Off
          6. 9.3.1.7.6 Right Leg Drive (RLD) DC Bias Circuit
            1. 9.3.1.7.6.1 WCT as RLD
            2. 9.3.1.7.6.2 RLD Configuration with Multiple Devices
          7. 9.3.1.7.7 Pace Detect
            1. 9.3.1.7.7.1 Software Approach
            2. 9.3.1.7.7.2 External Hardware Approach
          8. 9.3.1.7.8 Respiration
            1. 9.3.1.7.8.1 External Respiration Circuitry (RESP_CTRL = 01b)
            2. 9.3.1.7.8.2 Internal Respiration Circuitry with Internal Clock (RESP_CTRL = 10b, ADS129xR Only)
            3. 9.3.1.7.8.3 Internal Respiration Circuitry With User-Generated Signals (RESP_CTRL = 11b, ADS129xR Only)
      2. 9.3.2 Digital Functionality
        1. 9.3.2.1 GPIO Pins (GPIO[4:1])
        2. 9.3.2.2 Power-Down Pin (PWDN)
        3. 9.3.2.3 Reset (RESET Pin and Reset Command)
        4. 9.3.2.4 Digital Decimation Filter
          1. 9.3.2.4.1 Sinc Filter Stage (sinx / x)
        5. 9.3.2.5 Clock
    4. 9.4 Device Functional Modes
      1. 9.4.1 Data Acquisition
        1. 9.4.1.1 Start Mode
          1. 9.4.1.1.1 Settling Time
        2. 9.4.1.2 Data Ready Pin (DRDY)
        3. 9.4.1.3 Data Retrieval
          1. 9.4.1.3.1 Status Word
          2. 9.4.1.3.2 Readback Length
          3. 9.4.1.3.3 Data Format
        4. 9.4.1.4 Single-Shot Mode
        5. 9.4.1.5 Continuous Conversion Mode
      2. 9.4.2 Multiple-Device Configuration
        1. 9.4.2.1 Cascade Configuration
        2. 9.4.2.2 Daisy-Chain Configuration
    5. 9.5 Programming
      1. 9.5.1 SPI Interface
        1. 9.5.1.1 Chip Select Pin (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
          1. 9.5.1.2.1 SCLK Clocking Methods
        3. 9.5.1.3 Data Input Pin (DIN)
        4. 9.5.1.4 Data Output Pin (DOUT)
      2. 9.5.2 SPI Command Definitions
        1. 9.5.2.1  WAKEUP: Exit Standby Mode
        2. 9.5.2.2  STANDBY: Enter Standby Mode
        3. 9.5.2.3  RESET: Reset Registers to Default Values
        4. 9.5.2.4  START: Start Conversions
        5. 9.5.2.5  STOP: Stop Conversions
        6. 9.5.2.6  RDATAC: Read Data Continuous
        7. 9.5.2.7  SDATAC: Stop Read Data Continuous
        8. 9.5.2.8  RDATA: Read Data
        9. 9.5.2.9  Sending Multibyte Commands
        10. 9.5.2.10 RREG: Read From Register
        11. 9.5.2.11 WREG: Write to Register
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1  ID: ID Control Register (address = 00h) (reset = xxh)
        2. 9.6.1.2  CONFIG1: Configuration Register 1 (address = 01h) (reset = 06h)
        3. 9.6.1.3  CONFIG2: Configuration Register 2 (address = 02h) (reset = 40h)
        4. 9.6.1.4  CONFIG3: Configuration Register 3 (address = 03h) (reset = 40h)
        5. 9.6.1.5  LOFF: Lead-Off Control Register (address = 04h) (reset = 00h)
        6. 9.6.1.6  CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 00h)
        7. 9.6.1.7  RLD_SENSP: RLD Positive Signal Derivation Register (address = 0Dh) (reset = 00h)
        8. 9.6.1.8  RLD_SENSN: RLD Negative Signal Derivation Register (address = 0Eh) (reset = 00h)
        9. 9.6.1.9  LOFF_SENSP: Positive Signal Lead-Off Detection Register (address = 0Fh) (reset = 00h)
        10. 9.6.1.10 LOFF_SENSN: Negative Signal Lead-Off Detection Register (address = 10h) (reset = 00h)
        11. 9.6.1.11 LOFF_FLIP: Lead-Off Flip Register (address = 11h) (reset = 00h)
        12. 9.6.1.12 LOFF_STATP: Lead-Off Positive Signal Status Register (address = 12h) (reset = 00h)
        13. 9.6.1.13 LOFF_STATN: Lead-Off Negative Signal Status Register (address = 13h) (reset = 00h)
        14. 9.6.1.14 GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh)
        15. 9.6.1.15 PACE: Pace Detect Register (address = 15h) (reset = 00h)
        16. 9.6.1.16 RESP: Respiration Control Register (address = 16h) (reset = 00h)
        17. 9.6.1.17 CONFIG4: Configuration Register 4 (address = 17h) (reset = 00h)
        18. 9.6.1.18 WCT1: Wilson Central Terminal and Augmented Lead Control Register (address = 18h) (reset = 00h)
        19. 9.6.1.19 WCT2: Wilson Central Terminal Control Register (address = 18h) (reset = 00h)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Setting the Device for Basic Data Capture
        1. 10.1.1.1 Lead-Off
        2. 10.1.1.2 Right Leg Drive
        3. 10.1.1.3 Pace Detection
      2. 10.1.2 Establishing the Input Common-Mode
      3. 10.1.3 Antialiasing
    2. 10.2 Typical Applications
      1. 10.2.1 ADS129xR Respiration Measurement Using Internal Modulation Circuitry
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Software-Based Artificial Pacemaker Detection Using the PACEOUT Pins on the ADS129x
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Sequencing
    2. 11.2 Connecting to Unipolar (3 V or 1.8 V) Supplies
    3. 11.3 Connecting to Bipolar (±1.5 V or ±1.8 V) Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Parameter Measurement Information

8.1 Noise Measurements

NOTE

The ADS129xR channel performance differs from the ADS129x in regards to respiration circuitry found on channel one. Unless otherwise noted, ADS129x refers to all specifications and functional descriptions of the ADS1294, ADS1296, ADS1298, ADS1294R, ADS1296R, and ADS1298R. ADS129xR refers to all specifications and functional descriptions of only the ADS1294R, ADS1296R, and ADS1298R.

Optimize the ADS129x noise performance by adjusting the data rate and PGA setting. Reduce the data rate to increase the averaging, and the noise drops correspondingly. Increase the PGA value to reduce the input-referred noise. This lowered noise level is particularly useful when measuring low-level biopotential signals. Table 1 and Table 2 summarize the noise performance of the ADS129x in high-resolution (HR) mode and low-power (LP) mode, respectively, with a 3-V analog power supply. Table 3 and Table 4 summarize the noise performance of the ADS129x in HR and LP modes, respectively, with a 5-V analog power supply. The data are representative of typical noise performance at TA = 25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate the RMS and peak-to-peak noise for each reading. For the two highest data rates, the noise is limited by quantization noise of the ADC and does not have a gaussian distribution. Thus, the ratio between rms noise and peak-to-peak noise is approximately 10. For the lower data rates, the ratio is approximately 6.6.

Table 1 to Table 4 show measurements taken with an internal reference. The data are also representative of the ADS129x noise performance when using a low-noise external reference such as the REF5025.

Table 1. Input-Referred Noise μVRMS (μVPP) in High-Resolution Mode
3-V Analog Supply and 2.4-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA
GAIN = 1		 PGA
GAIN = 2		 PGA
GAIN = 3		 PGA
GAIN = 4		 PGA
GAIN = 6		 PGA
GAIN = 8		 PGA
GAIN = 12
000 32000 8398 335 (3553) 168 (1701) 112 (1100) 85 (823) 58 (529) 42.5 (378) 28.6 (248)
001 16000 4193 56 (613) 28 (295) 18.8 (188) 14.3 (143) 9.7 (94) 7.4 (69) 5.2 (44.3)
010 8000 2096 12.4 (111) 6.5 (54) 4.5 (37.9) 3.5 (29.7) 2.6 (21.7) 2.2 (17.8) 1.8 (13.8)
011 4000 1048 6.1 (44.8) 3.2 (23.3) 2.4 (17.1) 1.9 (14) 1.5 (11.1) 1.3 (9.7) 1.2 (8.5)
100 2000 524 4.1 (27.8) 2.2 (15.4) 1.6 (11) 1.3 (9.1) 1.1 (7.3) 1 (6.5) 0.9 (6)
101 1000 262 2.9 (19) 1.6 (10.1) 1.2 (7.5) 1 (6.2) 0.8 (5) 0.7 (4.6) 0.6 (4.1)
110 500 131 2.1 (12.5) 1.1 (6.8) 0.9 (5.1) 0.7 (4.3) 0.6 (3.5) 0.5 (3.1) 0.5 (2.9)
(1) At least 1000 consecutive readings used to calculate the RMS and peak-to-peak noise values in this table.

Table 2. Input-Referred Noise μVRMS (μVPP) in Low-Power Mode
3-V Analog Supply and 2.4-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA
GAIN = 1		 PGA
GAIN = 2		 PGA
GAIN = 3		 PGA
GAIN = 4		 PGA
GAIN = 6		 PGA
GAIN = 8		 PGA
GAIN = 12
000 16000 4193 333 (3481) 166 (1836) 111 (1168) 84 (834) 56 (576) 42 (450) 28 (284)
001 8000 2096 56 (554) 28 (272) 19 (177) 14.3 (133) 9.7 (85) 7.4 (64) 5 (42.4)
010 4000 1048 12.5 (99) 6.5 (51) 4.5 (35) 3.4 (25.9) 2.4 (18.8) 2 (14.5) 1.5 (11.3)
011 2000 524 6.1 (41.8) 3.2 (22.2) 2.3 (15.9) 1.8 (12.1) 1.4 (9.3) 1.2 (7.8) 1 (6.7)
100 1000 262 4.1 (26.3) 2.2 (14.6) 1.6 (9.9) 1.3 (8.1) 1 (6.2) 0.8 (5.4) 0.7 (4.7)
101 500 131 3 (17.9) 1.6 (9.8) 1.1 (6.8) 0.9 (5.7) 0.7 (4.2) 0.6 (3.6) 0.5 (3.4)
110 250 65 2.1 (11.9) 1.1 (6.3) 0.8 (4.6) 0.7 (4) 0.5 (3) 0.5 (2.6) 0.4 (2.4)
(1) At least 1000 consecutive readings used to calculate the RMS and peak-to-peak noise values in this table.

Table 3. Input-Referred Noise μVRMS (μVPP) in High-Resolution Mode
5-V Analog Supply and 4-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA
GAIN = 1		 PGA
GAIN = 2		 PGA
GAIN = 3		 PGA
GAIN = 4		 PGA
GAIN = 6		 PGA
GAIN = 8		 PGA
GAIN = 12
000 32000 8398 521 (5388) 260 (2900) 173 (1946) 130 (1403) 87 (917) 65 (692) 44 (483)
001 16000 4193 86 (1252) 43 (633) 29 (402) 22 (298) 15 (206) 11 (141) 7 (91)
010 8000 2096 17 (207) 9 (112) 6 (71) 4 (57) 3 (36) 3 (29) 2 (18)
011 4000 1048 6.4 (48.2) 3.4 (25.9) 2.417.7) 1.9 (15.4) 1.5 (11.2) 1.3 (9.6) 1.1 (8.2)
100 2000 524 4.2 (29.9) 2.3 (15.9) 1.6 (11.1) 1.3 (9.3) 1 (7.5) 0.9 (6.6) 0.8 (5.8)
101 1000 262 2.9 (18.8) 1.6 (10.4) 1.1 (7.8) 0.9 (6.1) 0.7 (4.9) 0.6 (4.7) 0.6 (3.9)
110 500 131 2 (12.8) 1.1 (7.2) 0.8 (5.2) 0.7 (4) 0.5 (3.3) 0.5 (3.3) 0.4 (2.7)
(1) At least 1000 consecutive readings used to calculate the RMS and peak-to-peak noise values in this table.

Table 4. Input-Referred Noise μVRMS (μVPP) in Low-Power Mode
5-V Analog Supply and 4-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA
GAIN = 1		 PGA
GAIN = 2		 PGA
GAIN = 3		 PGA
GAIN = 4		 PGA
GAIN = 6		 PGA
GAIN = 8		 PGA
GAIN = 12
000 16000 4193 526 (5985) 263 (2953) 175 (1918) 132 (1410) 88 (896) 66 (681) 44 (458)
001 8000 2096 88 (1201) 44 (619) 29 (411) 22 (280) 15 (191) 11 (139) 7 (83)
010 4000 1048 17 (208) 9 (103) 6 (62) 4 (52) 3 (37) 2 (25) 2 (16)
011 2000 524 6 (41.1) 3.3 (23.3) 2.2 (15.5) 1.8 (12.3) 1.3 (9.8) 1.1 (7.8) 0.9 (6.5)
100 1000 262 4.1 (27.1) 2.3 (14.8) 1.5 (10.1) 1.2 (8.1) 0.9 (6) 0.8 (5.4) 0.7 (4.4)
101 500 131 2.9 (17.4) 1.6 (9.6) 1.1 (6.6) 0.9 (5.9) 0.7 (4.3) 0.6 (3.4) 0.5 (3.2)
110 250 65 2.1 (11.9) 1.1 (6.6) 0.8 (4.6) 0.6 (3.7) 0.5 (3) 0.4 (2.5) 0.4 (2.2)
(1) At least 1000 consecutive readings used to calculate the RMS and peak-to-peak noise values in this table.