SBAS499C July   2012  – January 2017 ADS1299 , ADS1299-4 , ADS1299-6

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Typical Characteristics
  8. 8 Parametric Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Functionality
        1. 9.3.1.1 Input Multiplexer
          1. 9.3.1.1.1 Device Noise Measurements
          2. 9.3.1.1.2 Test Signals (TestP and TestN)
          3. 9.3.1.1.3 Temperature Sensor (TempP, TempN)
          4. 9.3.1.1.4 Supply Measurements (MVDDP, MVDDN)
          5. 9.3.1.1.5 Lead-Off Excitation Signals (LoffP, LoffN)
          6. 9.3.1.1.6 Auxiliary Single-Ended Input
        2. 9.3.1.2 Analog Input
        3. 9.3.1.3 PGA Settings and Input Range
          1. 9.3.1.3.1 Input Common-Mode Range
          2. 9.3.1.3.2 Input Differential Dynamic Range
          3. 9.3.1.3.3 ADC ΔΣ Modulator
          4. 9.3.1.3.4 Reference
      2. 9.3.2 Digital Functionality
        1. 9.3.2.1 Digital Decimation Filter
          1. 9.3.2.1.1 Sinc Filter Stage (sinx / x)
        2. 9.3.2.2 Clock
        3. 9.3.2.3 GPIO
        4. 9.3.2.4 ECG and EEG Specific Features
          1. 9.3.2.4.1 Input Multiplexer (Rerouting the BIAS Drive Signal)
          2. 9.3.2.4.2 Input Multiplexer (Measuring the BIAS Drive Signal)
          3. 9.3.2.4.3 Lead-Off Detection
            1. 9.3.2.4.3.1 DC Lead-Off
            2. 9.3.2.4.3.2 AC Lead-Off (One Time or Periodic)
          4. 9.3.2.4.4 Bias Lead-Off
          5. 9.3.2.4.5 Bias Drive (DC Bias Circuit)
            1. 9.3.2.4.5.1 Bias Configuration with Multiple Devices
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start
        1. 9.4.1.1 Settling Time
      2. 9.4.2 Reset (RESET)
      3. 9.4.3 Power-Down (PWDN)
      4. 9.4.4 Data Retrieval
        1. 9.4.4.1 Data Ready (DRDY)
        2. 9.4.4.2 Reading Back Data
      5. 9.4.5 Continuous Conversion Mode
      6. 9.4.6 Single-Shot Mode
    5. 9.5 Programming
      1. 9.5.1 Data Format
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Chip Select (CS)
        2. 9.5.2.2 Serial Clock (SCLK)
        3. 9.5.2.3 Data Input (DIN)
        4. 9.5.2.4 Data Output (DOUT)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  Sending Multi-Byte Commands
        2. 9.5.3.2  WAKEUP: Exit STANDBY Mode
        3. 9.5.3.3  STANDBY: Enter STANDBY Mode
        4. 9.5.3.4  RESET: Reset Registers to Default Values
        5. 9.5.3.5  START: Start Conversions
        6. 9.5.3.6  STOP: Stop Conversions
        7. 9.5.3.7  RDATAC: Read Data Continuous
        8. 9.5.3.8  SDATAC: Stop Read Data Continuous
        9. 9.5.3.9  RDATA: Read Data
        10. 9.5.3.10 RREG: Read From Register
        11. 9.5.3.11 WREG: Write to Register
    6. 9.6 Register Maps
      1. 9.6.1 User Register Description
        1. 9.6.1.1  ID: ID Control Register (address = 00h) (reset = xxh)
        2. 9.6.1.2  CONFIG1: Configuration Register 1 (address = 01h) (reset = 96h)
        3. 9.6.1.3  CONFIG2: Configuration Register 2 (address = 02h) (reset = C0h)
        4. 9.6.1.4  CONFIG3: Configuration Register 3 (address = 03h) (reset = 60h)
        5. 9.6.1.5  LOFF: Lead-Off Control Register (address = 04h) (reset = 00h)
        6. 9.6.1.6  CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 61h)
        7. 9.6.1.7  BIAS_SENSP: Bias Drive Positive Derivation Register (address = 0Dh) (reset = 00h)
        8. 9.6.1.8  BIAS_SENSN: Bias Drive Negative Derivation Register (address = 0Eh) (reset = 00h)
        9. 9.6.1.9  LOFF_SENSP: Positive Signal Lead-Off Detection Register (address = 0Fh) (reset = 00h)
        10. 9.6.1.10 LOFF_SENSN: Negative Signal Lead-Off Detection Register (address = 10h) (reset = 00h)
        11. 9.6.1.11 LOFF_FLIP: Lead-Off Flip Register (address = 11h) (reset = 00h)
        12. 9.6.1.12 LOFF_STATP: Lead-Off Positive Signal Status Register (address = 12h) (reset = 00h)
        13. 9.6.1.13 LOFF_STATN: Lead-Off Negative Signal Status Register (address = 13h) (reset = 00h)
        14. 9.6.1.14 GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh)
        15. 9.6.1.15 MISC1: Miscellaneous 1 Register (address = 15h) (reset = 00h)
        16. 9.6.1.16 MISC2: Miscellaneous 2 (address = 16h) (reset = 00h)
        17. 9.6.1.17 CONFIG4: Configuration Register 4 (address = 17h) (reset = 00h)
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Setting the Device for Basic Data Capture
        1. 10.1.2.1 Lead-Off
        2. 10.1.2.2 Bias Drive
      3. 10.1.3 Establishing the Input Common-Mode
      4. 10.1.4 Multiple Device Configuration
        1. 10.1.4.1 Cascaded Mode
        2. 10.1.4.2 Daisy-Chain Mode
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Sequencing
    2. 11.2 Connecting the Device to Unipolar (5 V and 3.3 V) Supplies
    3. 11.3 Connecting the Device to Bipolar (±2.5 V and 3.3 V) Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Up to Eight Low-Noise PGAs and Eight High-Resolution Simultaneous-Sampling ADCs
  • Input-Referred Noise: 1 μVPP (70-Hz BW)
  • Input Bias Current: 300 pA
  • Data Rate: 250 SPS to 16 kSPS
  • CMRR: –110 dB
  • Programmable Gain: 1, 2, 4, 6, 8, 12, or 24
  • Unipolar or Bipolar Supplies:
    • Analog: 4.75 V to 5.25 V
    • Digital: 1.8 V to 3.6 V
  • Built-In Bias Drive Amplifier,
    Lead-Off Detection, Test Signals
  • Built-In Oscillator
  • Internal or External Reference
  • Flexible Power-Down, Standby Mode
  • Pin-Compatible with the ADS129x
  • SPI-Compatible Serial Interface
  • Operating Temperature Range: –40°C to +85°C

2 Applications

  • Medical Instrumentation Including:
    • Electroencephalogram (EEG) Study
    • Fetal Electrocardiography (ECG)
    • Sleep Study Monitor
    • Bispectral Index (BIS)
    • Evoked Audio Potential (EAP)

3 Description

The ADS1299-4, ADS1299-6, and ADS1299 devices are a family of four-, six-, and eight-channel, low-noise, 24-bit, simultaneous-sampling delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with a built-in programmable gain amplifier (PGA), internal reference, and an onboard oscillator. The ADS1299-x incorporates all commonly-required features for extracranial electroencephalogram (EEG) and electrocardiography (ECG) applications. With its high levels of integration and exceptional performance, the ADS1299-x enables the creation of scalable medical instrumentation systems at significantly reduced size, power, and overall cost.

The ADS1299-x has a flexible input multiplexer per channel that can be independently connected to the internally-generated signals for test, temperature, and lead-off detection. Additionally, any configuration of input channels can be selected for derivation of the patient bias output signal. Optional SRB pins are available to route a common signal to multiple inputs for a referential montage configuration. The ADS1299-x operates at data rates from 250 SPS to 16 kSPS. Lead-off detection can be implemented internal to the device using an excitation current sink or source.

Multiple ADS1299-4, ADS1299-6, or ADS1299 devices can be cascaded in high channel count systems in a daisy-chain configuration. The ADS1299-x is offered in a TQFP-64 package specified from –40°C to +85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS1299-x TQFP (64) 10.00 mm × 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

ADS1299 ADS1299-4 ADS1299-6 alt_sbas499.gif

4 Revision History

Changes from B Revision (October 2016) to C Revision

  • Changed Maximum Junction parameter name to Junction in Absolute Maximum Ratings tableGo
  • Changed Recommended Operating Conditions table: changed free-air to ambient in conditions statement, changed specifications of Input voltage parameter, and added VCM and fCLK symbolsGo
  • Changed conditions statement of Electrical Characteristics table: added TA to temperature conditions, moved DVDD condition to after AVDD – AVSS condition Go
  • Changed Input bias current parameter test conditions from input to InxP and INxNGo
  • Changed Drift parameter unit from ppm to ppm/°C and changed Internal clock accuracy parameter test conditions from –40°C ≤ TA ≤ +85°C to TA = –40°C to +85°C in Electrical Characteristics tableGo
  • Changed IAVDD and IDVDD parameters [deleted (normal mode) from parameter names and added Normal mode to test conditions], and deleted Quiescent from Power dissipation parameter name in Electrical Characteristics tableGo
  • Changed free-air to ambient in conditions statement of Timing Requirements: Serial Interface tableGo
  • Changed Analog Input section Go
  • Changed Table 9 cross-reference to Table 7 in Settling Time sectionGo
  • Changed Ideal Output Code versus Input Signal table: changed all VREF in first column to FS in and deleted footnote 1 Go
  • Changed reset settings of bits 4 and 3 in bit register of CONFIG1 registerGo
  • Changed reset value settings of bits 7 to 5 in CONFIG2 register: split cells apartGo
  • Changed reset value settings of bits 6 to 5 in CONFIG3 register: split cells apart Go
  • Changed AVDD – AVSS to AVDD + AVSS in description of bit 3 in Configuration Register 3 Field DescriptionsGo
  • Changed Lead-Off Control Register Field Descriptions table: changed 01 bit setting of bits 3:2 to 24 nA from 12 nA changed description of bits 1:0Go
  • Changed Unused Inputs and Outputs section: added DRDY description, deleted statement of not floating unused digital inputs Go
  • Deleted second Layout Guidelines sub-section from Layout section Go

Changes from A Revision (August 2012) to B Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Added ADS1299-4 and ADS1299-6 to documentGo
  • Added Go
  • Deleted Low Power Features bullet Go
  • Changed extracranial electroencephalogram (EEG) in Applications and Description sectionsGo
  • Deleted last Applications bullet Go
  • Changed Description section: added sentence on SRB pins, changed last sentence of second paragraphGo
  • Changed ADS1299 family to ADS1299-x throughout document Go
  • Changed Block Diagram: added dotted boxes Go
  • Changed specifications for Lead-Off Detect, Frequency parameter of Electrical Characteristics tableGo
  • Added specifications for ADS1299-4 and ADS1299-6 in Supply Current (Bias Turned Off) and Power Dissipation (Analog Supply = 5 V, Bias Amplifiers Turned Off) sections of Electrical Characteristics tableGo
  • Changed Noise Measurements sectionGo
  • Changed Functional Block Diagram to show channels 5-8 not covered in ADS1299-4 and channels 7-8 not covered in ADS1299-6Go
  • Changed INxP and INxN pins in Figure 18 Go
  • Changed Figure 23: changed PgaP, PgaN to PGAp, PGAn Go
  • Changed Input Common-Mode Range section: changed input common-mode range description Go
  • Changed differential input voltage range in the Input Differential Dynamic Range sectionGo
  • Changed Figure 34: MUX8[2:0] = 010 on IN8N, and BIAS_MEAS = 1 on BIASINGo
  • Changed first sentence of second paragraph in Lead-Off Detection sectionGo
  • Changed AC Lead-Off (One Time or Periodic) sectionGo
  • Changed Bias Lead-Off sectionGo
  • Changed title of Figure 38 and power-down description in Bias Drive (DC Bias Circuit) sectionGo
  • Changed START Opcode to START in Figure 39Go
  • Changed Reset (RESET) section for clarityGo
  • Changed title, first paragraph, START Opcode and STOP Opcode to START and STOP (Figure 42), and STOP Opcode to STOP Command (Figure 43) in Continuous Conversion Mode sectionGo
  • Added last sentence to Data Input (DIN) sectionGo
  • Added cross-reference to the Sending Multi-Byte Commands section in RDATAC: Read Data Continuous section Go
  • Changed RDATAC Opcode to RDATAC in Figure 46Go
  • Changed RDATA Opcode to RDATA in Figure 46Go
  • Changed description of SCLK rate restrictions, OPCODE 1 and OPCODE 2 to BYTE 1 and BYTE 2 in Figure 48 of RREG: Read From Register sectionGo
  • Changed footnotes 1 and 2 and added more cross-references to footnotes in rows 0Dh to 11h in Table 11 Go
  • Changed register description and description of bit 5 in MISC1: Miscellaneous 1 Register sectionGo
  • Changed output names in Figure 68 from RA, LA, and RL to Electrode 1, Electrode 2, and BIAS Electrode, respectivelyGo
  • Changed Power-Up Sequencing sectionGo

Changes from * Revision (July 2012) to A Revision

  • Changed product column of Family and Ordering Information table Go