SBAS499C July   2012  – January 2017 ADS1299 , ADS1299-4 , ADS1299-6

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Typical Characteristics
  8. 8 Parametric Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Functionality
        1. 9.3.1.1 Input Multiplexer
          1. 9.3.1.1.1 Device Noise Measurements
          2. 9.3.1.1.2 Test Signals (TestP and TestN)
          3. 9.3.1.1.3 Temperature Sensor (TempP, TempN)
          4. 9.3.1.1.4 Supply Measurements (MVDDP, MVDDN)
          5. 9.3.1.1.5 Lead-Off Excitation Signals (LoffP, LoffN)
          6. 9.3.1.1.6 Auxiliary Single-Ended Input
        2. 9.3.1.2 Analog Input
        3. 9.3.1.3 PGA Settings and Input Range
          1. 9.3.1.3.1 Input Common-Mode Range
          2. 9.3.1.3.2 Input Differential Dynamic Range
          3. 9.3.1.3.3 ADC ΔΣ Modulator
          4. 9.3.1.3.4 Reference
      2. 9.3.2 Digital Functionality
        1. 9.3.2.1 Digital Decimation Filter
          1. 9.3.2.1.1 Sinc Filter Stage (sinx / x)
        2. 9.3.2.2 Clock
        3. 9.3.2.3 GPIO
        4. 9.3.2.4 ECG and EEG Specific Features
          1. 9.3.2.4.1 Input Multiplexer (Rerouting the BIAS Drive Signal)
          2. 9.3.2.4.2 Input Multiplexer (Measuring the BIAS Drive Signal)
          3. 9.3.2.4.3 Lead-Off Detection
            1. 9.3.2.4.3.1 DC Lead-Off
            2. 9.3.2.4.3.2 AC Lead-Off (One Time or Periodic)
          4. 9.3.2.4.4 Bias Lead-Off
          5. 9.3.2.4.5 Bias Drive (DC Bias Circuit)
            1. 9.3.2.4.5.1 Bias Configuration with Multiple Devices
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start
        1. 9.4.1.1 Settling Time
      2. 9.4.2 Reset (RESET)
      3. 9.4.3 Power-Down (PWDN)
      4. 9.4.4 Data Retrieval
        1. 9.4.4.1 Data Ready (DRDY)
        2. 9.4.4.2 Reading Back Data
      5. 9.4.5 Continuous Conversion Mode
      6. 9.4.6 Single-Shot Mode
    5. 9.5 Programming
      1. 9.5.1 Data Format
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Chip Select (CS)
        2. 9.5.2.2 Serial Clock (SCLK)
        3. 9.5.2.3 Data Input (DIN)
        4. 9.5.2.4 Data Output (DOUT)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  Sending Multi-Byte Commands
        2. 9.5.3.2  WAKEUP: Exit STANDBY Mode
        3. 9.5.3.3  STANDBY: Enter STANDBY Mode
        4. 9.5.3.4  RESET: Reset Registers to Default Values
        5. 9.5.3.5  START: Start Conversions
        6. 9.5.3.6  STOP: Stop Conversions
        7. 9.5.3.7  RDATAC: Read Data Continuous
        8. 9.5.3.8  SDATAC: Stop Read Data Continuous
        9. 9.5.3.9  RDATA: Read Data
        10. 9.5.3.10 RREG: Read From Register
        11. 9.5.3.11 WREG: Write to Register
    6. 9.6 Register Maps
      1. 9.6.1 User Register Description
        1. 9.6.1.1  ID: ID Control Register (address = 00h) (reset = xxh)
        2. 9.6.1.2  CONFIG1: Configuration Register 1 (address = 01h) (reset = 96h)
        3. 9.6.1.3  CONFIG2: Configuration Register 2 (address = 02h) (reset = C0h)
        4. 9.6.1.4  CONFIG3: Configuration Register 3 (address = 03h) (reset = 60h)
        5. 9.6.1.5  LOFF: Lead-Off Control Register (address = 04h) (reset = 00h)
        6. 9.6.1.6  CHnSET: Individual Channel Settings (n = 1 to 8) (address = 05h to 0Ch) (reset = 61h)
        7. 9.6.1.7  BIAS_SENSP: Bias Drive Positive Derivation Register (address = 0Dh) (reset = 00h)
        8. 9.6.1.8  BIAS_SENSN: Bias Drive Negative Derivation Register (address = 0Eh) (reset = 00h)
        9. 9.6.1.9  LOFF_SENSP: Positive Signal Lead-Off Detection Register (address = 0Fh) (reset = 00h)
        10. 9.6.1.10 LOFF_SENSN: Negative Signal Lead-Off Detection Register (address = 10h) (reset = 00h)
        11. 9.6.1.11 LOFF_FLIP: Lead-Off Flip Register (address = 11h) (reset = 00h)
        12. 9.6.1.12 LOFF_STATP: Lead-Off Positive Signal Status Register (address = 12h) (reset = 00h)
        13. 9.6.1.13 LOFF_STATN: Lead-Off Negative Signal Status Register (address = 13h) (reset = 00h)
        14. 9.6.1.14 GPIO: General-Purpose I/O Register (address = 14h) (reset = 0Fh)
        15. 9.6.1.15 MISC1: Miscellaneous 1 Register (address = 15h) (reset = 00h)
        16. 9.6.1.16 MISC2: Miscellaneous 2 (address = 16h) (reset = 00h)
        17. 9.6.1.17 CONFIG4: Configuration Register 4 (address = 17h) (reset = 00h)
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Setting the Device for Basic Data Capture
        1. 10.1.2.1 Lead-Off
        2. 10.1.2.2 Bias Drive
      3. 10.1.3 Establishing the Input Common-Mode
      4. 10.1.4 Multiple Device Configuration
        1. 10.1.4.1 Cascaded Mode
        2. 10.1.4.2 Daisy-Chain Mode
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Sequencing
    2. 11.2 Connecting the Device to Unipolar (5 V and 3.3 V) Supplies
    3. 11.3 Connecting the Device to Bipolar (±2.5 V and 3.3 V) Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Parametric Measurement Information

8.1 Noise Measurements

NOTE

Unless otherwise noted, ADS1299-x refers to all specifications and functional descriptions of the ADS1299-4, ADS1299-6, and ADS1299.

Optimize the ADS1299-x noise performance by adjusting the data rate and PGA setting. Reduce the data rate to increase the averaging, and the noise drops correspondingly. Increase the PGA value to reduce the input-referred noise. This lowered noise level is particularly useful when measuring low-level biopotential signals. Table 1 to Table 4 summarize the ADS1299-x noise performance with a 5-V analog power supply. The data are representative of typical noise performance at TA = +25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. A minimum of 1000 consecutive readings are used to calculate the RMS and peak-to-peak noise for each reading. For the lower data rates, the ratio is approximately 6.6.

Table 1 shows measurements taken with an internal reference. The data are also representative of the ADS1299-x noise performance when using a low-noise external reference such as the REF5045.

Table 1, Table 2, Table 3, and Table 4 list the input-referred noise in units of μVRMS and μVPP for the conditions shown. The corresponding data in units of effective number of bits (ENOB) where ENOB for the RMS noise is defined as in Equation 1:

Equation 1. ADS1299 ADS1299-4 ADS1299-6 q_enob_sbas499.gif

Noise-free bits for the peak-to-peak noise are calculated with the same method.

The dynamic range data in Table 1, Table 2, Table 3, and Table 4 are calculated using Equation 2:

Equation 2. ADS1299 ADS1299-4 ADS1299-6 q_dynamicrange_sbas499.gif

Table 1. Input-Referred Noise (μVRMS, μVPP) in Normal Mode
5-V Analog Supply and 4.5-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA
GAIN = 1		 PGA
GAIN = 2
μVRMS μVPP DYNAMIC RANGE (dB) NOISE-FREE BITS ENOB μVRMS μVPP DYNAMIC RANGE (dB) NOISE-FREE BITS ENOB
000 16000 4193 21.70 151.89 103.3 15.85 17.16 10.85 75.94 103.3 15.85 17.16
001 8000 2096 6.93 48.53 113.2 17.50 18.81 3.65 25.52 112.8 17.43 18.74
010 4000 1048 4.33 30.34 117.3 18.18 19.49 2.28 15.95 116.9 18.11 19.41
011 2000 524 3.06 21.45 120.3 18.68 19.99 1.61 11.29 119.9 18.60 19.91
100 1000 262 2.17 15.17 123.3 19.18 20.49 1.14 7.98 122.9 19.10 20.41
101 500 131 1.53 10.73 126.3 19.68 20.99 0.81 5.65 125.9 19.60 20.91
110 250 65 1.08 7.59 129.3 20.18 21.48 0.57 3.99 128.9 20.10 21.41
111 n/a n/a — — — — — — — — — —
(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

Table 2. Input-Referred Noise (μVRMS, μVPP) in Normal Mode
5-V Analog Supply and 4.5-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA
GAIN = 4		 PGA
GAIN = 6
μVRMS μVPP DYNAMIC RANGE (dB) NOISE-FREE BITS ENOB μVRMS μVPP DYNAMIC RANGE (dB) NOISE-FREE BITS ENOB
000 16000 4193 5.60 39.23 103.0 15.81 17.12 3.87 27.10 102.7 15.76 17.06
001 8000 2096 1.98 13.87 112.1 17.31 18.62 1.31 9.19 112.1 17.32 18.62
010 4000 1048 1.24 8.66 116.1 17.99 19.29 0.93 6.50 115.1 17.82 19.12
011 2000 524 0.88 6.13 119.2 18.49 19.79 0.66 4.60 118.1 18.32 19.62
100 1000 262 0.62 4.34 122.2 18.99 20.29 0.46 3.25 121.1 18.81 20.12
101 500 131 0.44 3.07 125.2 19.49 20.79 0.33 2.30 124.1 19.31 20.62
110 250 65 0.31 2.16 128.2 19.99 21.30 0.23 1.62 127.2 19.82 21.13
111 n/a n/a — — — — — — — — — —
(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

Table 3. Input-Referred Noise (μVRMS, μVPP) in Normal Mode
5-V Analog Supply and 4.5-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA
GAIN = 8		 PGA
GAIN = 12
μVRMS μVPP DYNAMIC RANGE (dB) NOISE-FREE BITS ENOB μVRMS μVPP DYNAMIC RANGE (dB) NOISE-FREE BITS ENOB
000 16000 4193 3.05 21.32 102.3 15.69 16.99 2.27 15.89 101.3 15.53 16.83
001 8000 2096 1.11 7.80 111.0 17.14 18.45 0.92 6.41 109.2 16.84 18.14
010 4000 1048 0.79 5.52 114.0 17.64 18.95 0.65 4.53 112.2 17.34 18.64
011 2000 524 0.56 3.90 117.1 18.14 19.44 0.46 3.20 115.2 17.84 19.14
100 1000 262 0.39 2.76 120.1 18.64 19.94 0.32 2.26 118.3 18.34 19.65
101 500 131 0.28 1.95 123.1 19.14 20.44 0.23 1.61 121.2 18.83 20.14
110 250 65 0.20 1.38 126.1 19.64 20.95 0.16 1.13 124.3 19.34 20.65
111 n/a n/a — — — — — — — — — —
(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.

Table 4. Input-Referred Noise (μVRMS, μVPP) in Normal Mode
5-V Analog Supply and 4.5-V Reference(1)

DR BITS OF CONFIG1 REGISTER OUTPUT DATA RATE (SPS) –3-dB BANDWIDTH (Hz) PGA
GAIN = 24
μVRMS μVPP DYNAMIC RANGE (dB) NOISE-FREE BITS ENOB
000 16000 4193 1.66 11.64 98.0 14.98 16.28
001 8000 2096 0.80 5.57 104.4 16.04 17.35
010 4000 1048 0.56 3.94 107.4 16.54 17.84
011 2000 524 0.40 2.79 110.4 17.04 18.35
100 1000 262 0.28 1.97 113.5 17.54 18.85
101 500 131 0.20 1.39 116.5 18.04 19.35
110 250 65 0.14 0.98 119.5 18.54 19.85
111 n/a n/a — — — — —
(1) At least 1000 consecutive readings were used to calculate the RMS and peak-to-peak noise values in this table.