SBAS590E March 2016 – June 2020 ADS131A02 , ADS131A04
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
This register configures the ADC clocking and sets the internal clock dividers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKSRC | 0 | 0 | 0 | CLK_DIV[2:0] | 0 | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-4h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLKSRC | R/W | 0h | ADC clock source.
This bit selects the source for ICLK; see the Clock section for more information on ADC clocking. 0 : XTAL1/CLKIN pin or XTAL1/CLKIN and XTAL2 pins (default) 1 : SCLK pin |
6:4 | Reserved | R/W | 0h | Reserved.
Always write 0h. |
3:1 | CLK_DIV[2:0] | R/W | 4h | CLKIN divider ratio.
These bits set the CLKIN divider ratio to generate the internal fICLK frequency. ICLK is used as the fSCLK output when the ADC is operating in synchronous master mode. 000 : Reserved 001 : fICLK = fCLKIN / 2 010 : fICLK = fCLKIN / 4 011 : fICLK = fCLKIN / 6 100 : fICLK = fCLKIN / 8 (default) 101 : fICLK = fCLKIN / 10 110 : fICLK = fCLKIN / 12 111 : fICLK = fCLKIN / 14 |
0 | Reserved | R/W | 0h | Reserved.
Always write 0. |