The ADS131B02-Q1 is a low-power, two-channel, simultaneous-sampling, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC) with a low-drift internal reference voltage. The dynamic range, size, feature set, and power consumption are optimized for cost-sensitive applications requiring simultaneous sampling.

The ADS131B02-Q1 requires both analog and digital supplies. The analog power supply (AVDD – AGND) can operate between 2.7 V and 3.6 V. An integrated negative charge pump allows absolute input voltages as low as 0.3 V below AGND, which enables measurements of input signals varying around ground with a unipolar power supply. The digital power supply (DVDD – DGND) can operate between 2.7 V and 3.6 V. The device features a high input impedance programmable gain amplifier (PGA) with gains up to 128. The ADC receives its reference voltage from an integrated 1.2-V reference. The device allows differential input voltages as large as the reference. Three power-scaling modes allow designers to trade power consumption for noise performance.

Each channel on the ADS131B02-Q1 contains a digital decimation filter that demodulates the output of the ΔΣ modulators. The filter enables data rates as high as 32 kSPS per channel in high-resolution mode. Offset and gain calibration registers can be programmed to automatically adjust output samples for measured offset and gain errors. The Section 8.2 provides a detailed diagram of the ADS131B02-Q1.

The device communicates via a serial peripheral interface (SPI)-compatible interface. Several SPI commands and internal registers control the operation of the ADS131B02-Q1. Other devices can be added to the same SPI bus by adding discrete CS control lines. The SYNC/RESET pin can be used to synchronize conversions between multiple ADS131B02-Q1 devices as well as to maintain synchronization with external events.