JAJSL29 September   2021 ADS131B02-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Internal Test Signals
      6. 8.3.6  Clocking
        1. 8.3.6.1 External Clock Using CLKIN Pin
        2. 8.3.6.2 Internal Oscillator
      7. 8.3.7  ΔΣ Modulator
      8. 8.3.8  Digital Filter
        1. 8.3.8.1 Digital Filter Implementation
          1. 8.3.8.1.1 Fast-Settling Filter
          2. 8.3.8.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.8.2 Digital Filter Characteristic
      9. 8.3.9  Calibration Registers
      10. 8.3.10 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Synchronization
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  SPI Communication Frames
        7. 8.5.1.7  SPI Communication Words
        8. 8.5.1.8  Short SPI Frames
        9. 8.5.1.9  Communication Cyclic Redundancy Check (CRC)
        10. 8.5.1.10 SPI Timeout
      2. 8.5.2 ADC Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0110 0110)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 Register Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Troubleshooting
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Minimum Interface Connections
      5. 9.1.5 Multiple Device Configuration
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 CAP Pin Capacitor Requirement
    2. 10.2 Power-Supply Sequencing
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 3.3 V, DVDD = 3.3 V, external clock, fCLKIN = 8.192 MHz, high-resolution mode, all channels, all gains, data rate = 4 kSPS, all channels enabled, and global-chop mode disabled (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Zin Differential input impedance Global-chop disabled 25 MΩ
Global-chop enabled 300
All power modes, all data rates See Table 8-2
Absolute input current Global-chop disabled, VAINxP = VAINxN = 0 V ±1 nA
Global-chop enabled, VAINxP = VAINxN = 0 V ±1
Differential input current Global-chop disabled, VAINxP = VAINxN = 0 V ±50 pA
Global-chop enabled, VAINxP = VAINxN = 0 V ±30
ADC CHARACTERISTICS
Resolution 24 Bits
Gain settings 1, 2, 4, 8, 16, 32, 64, 128
fDATA Data rate High-resolution mode, fCLKIN = 8.192 MHz 250 32k SPS
Low-power mode, fCLKIN = 4.096 MHz 125 16k
Very-low-power mode, fCLKIN = 2.048 MHz 62.5 8k
ADC PERFORMANCE
INL Integral nonlinearity (best fit) Differential-ended input 10 ppm of FSR
Offset error (input referred) Global-chop disabled –800 ±200 800 µV
Global-chop enabled –4 ±0.4 4
Offset drift Global-chop disabled, gain = 1 to 4 100 500 nV/°C
Global-chop disabled, gain = 8 to 128 50 200
Global-chop enabled 10 30
Offset error long-term drift 1000 hours at TA = 85°C, global-chop disabled 0.8 μV
1000 hours at TA = 85°C, global-chop enabled 0.25
Gain error Including error of internal voltage reference, TA = 25°C –0.7% ±0.2% 0.7%
Gain drift Including drift of internal voltage reference,
TA = –40°C to +85°C, gain = 1 to 4		 8 30 ppm/°C
Including drift of internal voltage reference,
TA = –40°C to +85°C, gain = 8 to 128		 7 25
Including drift of internal voltage reference,
TA = –40°C to +125°C		 13 40
Gain error long-term drift 1000 hours at TA = 85°C, gain = 1,
including drift of internal voltage reference		 250 ppm
CMRR Common-mode rejection ratio At dc, global-chop disabled, gain = 1 96 dB
At dc, global-chop enabled, gain = 1 128
fCM = 50 Hz or 60 Hz, global-chop disabled, gain = 1 89
fCM = 50 Hz or 60 Hz, global-chop enabled, gain = 1 106
PSRR Power-supply rejection ratio AVDD at dc, global-chop disabled, gain = 1 81 dB
AVDD at dc, global-chop enabled, gain = 1 116
DVDD at dc, global-chop disabled, gain = 1 109
DVDD at dc, global-chop enabled, gain = 1 117
Input-referred noise Gain = 1 5.42 µVRMS
Gain = 8 1.29
All gains, all data rates See Table 7-1
During fast start-up 1.5 mVRMS
Crosstalk fIN = 50 Hz or 60 Hz –120 dB
INTERNAL VOLTAGE REFERENCE
VREF Internal reference voltage 1.2 V
INTERNAL OSCILLATOR
fOSC Frequency 8.192 MHz
Accuracy –5% ±0.5% 2.5%
Frequency long-term drift 1000 hours at TA = 85°C 0.2%
DIGITAL INPUTS/OUTPUTS
VIL Logic input level, low DGND 0.2 DVDD V
VIH Logic input level, high 0.8 DVDD DVDD V
VOL Logic output level, low IOL = –1 mA 0.2 DVDD V
VOH Logic output level, high IOH = 1 mA 0.8 DVDD V
IIN Input current DGND < VDigital Input < DVDD –1 1 µA
POWER SUPPLY
IAVDD Analog supply current High-resolution mode, gain = 1, 2 2.9 3.6 mA
High-resolution mode, gain = 4 to 128 3.3 4.2
Low-power mode, gain = 1, 2 1.5 2
Low-power mode, gain = 4 to 128 1.7
Very-low-power mode, gain = 1, 2 0.8 1.2
Very-low-power mode, gain = 4 to 128 0.9
Standby mode 0.4 µA
Internal oscillator 140
IDVDD Digital supply current(1) High-resolution mode 0.3 0.4 mA
Low-power mode 0.15 0.2
Very-low-power mode 0.1 0.14
Standby mode(2) 1.2 µA
PD Power dissipation High-resolution mode, gain = 1, 2 10.6 13.2 mW
High-resolution mode, gain = 4 to 128 11.9 15.2
Low-power mode, gain = 1, 2 5.4 7.3
Very-low-power mode, gain = 1, 2 3 4.4
(1) Currents measured with SPI idle.
(2) External clock stopped.