JAJSPC7A December 2022 – August 2023 ADS131B23
PRODUCTION DATA
Table 8-25 lists the memory-mapped registers for the Registers registers. All register offset addresses not listed in Table 8-25 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Reset | Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |
---|---|---|---|---|---|---|---|---|---|---|
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | |||
SECTION 0 | ||||||||||
00h | ID | X | REV[7:0] | |||||||
ADC_COUNT[2:0] | DEVICE_ID[4:0] | |||||||||
01h | STATUS_MSB | 7FC8h | RESETn | SUPPLY_FAULTn | CLOCK_FAULTn | DIGITAL_FAULTn | OCC_FAULTn | SPI_CRC_FAULTn | SPI_TIMEOUTn | SCLK_COUNT_FAULTn |
REG_ACCESS_FAULTn | COMMAND_RESPONSE[3:0] | LOCK | CLOCK | MODE | ||||||
02h | STATUS_LSB | 0000h | SEQ2A_COUNT[1:0] | RESERVED | CONV1A_COUNT[1:0] | CONV1B_COUNT[1:0] | ||||
RESERVED | SEQ2A_ACTIVE | RESERVED | ||||||||
03h | SUPPLY_STATUS | FFFFh | AVDD_OVn | AVDD_UVn | IOVDD_OVn | IOVDD_UVn | DVDD_OVn | DVDD_UVn | AVDD_OSCn | IOVDD_OSCn |
DVDD_OSCn | AVDD_OTWn | IOVDD_OTWn | AVDD_CLn | IOVDD_CLn | AGNDA_DISCn | AGNDB_DISCn | DGND_DISCn | |||
04h | CLOCK_STATUS | FC07h | RESERVED | |||||||
RESERVED | MCLK_FAULTn | OSCD_WDn | MCLK_WDn | |||||||
05h | DIGITAL_STATUS | EC00h | REG_MAP1_CRC_FAULTn | REG_MAP2_CRC_FAULTn | REG_MAP3_CRC_FAULTn | RESERVED | MEM_MAP_CRC_FAULTn | OTP_BANK | RESERVED | |
RESERVED | ||||||||||
06h | OCC_STATUS | 000Fh | RESERVED | |||||||
RESERVED | OCCA_HTn | OCCA_LTn | OCCB_HTn | OCCB_LTn | ||||||
07h | GPI_DATA | 0000h | RESERVED | GPI4_DAT[1:0] | ||||||
GPI3_DAT[1:0] | GPI2_DAT[1:0] | GPI1_DAT[1:0] | GPI0_DAT[1:0] | |||||||
08h | GPIA_GPIB_DATA | 0000h | RESERVED | GPI1A_DAT[1:0] | GPI0A_DAT[1:0] | |||||
RESERVED | GPI1B_DAT[1:0] | GPI0B_DAT[1:0] | ||||||||
09h | CONVERSION_CTRL | 0000h | RESERVED | STARTA | RESERVED | STARTB | RESERVED | STOPA | RESERVED | STOPB |
RESERVED | SEQ2A_START | RESERVED | SEQ2A_STOP | RESERVED | ||||||
10h | SEQ2A_STEP0_DATA | 0000h | SEQ2A_STEP0_DAT[15:0] | |||||||
SEQ2A_STEP0_DAT[15:0] | ||||||||||
11h | SEQ2A_STEP1_DATA | 0000h | SEQ2A_STEP1_DAT[15:0] | |||||||
SEQ2A_STEP1_DAT[15:0] | ||||||||||
12h | SEQ2A_STEP2_DATA | 0000h | SEQ2A_STEP2_DAT[15:0] | |||||||
SEQ2A_STEP2_DAT[15:0] | ||||||||||
13h | SEQ2A_STEP3_DATA | 0000h | SEQ2A_STEP3_DAT[15:0] | |||||||
SEQ2A_STEP3_DAT[15:0] | ||||||||||
14h | SEQ2A_STEP4_DATA | 0000h | SEQ2A_STEP4_DAT[15:0] | |||||||
SEQ2A_STEP4_DAT[15:0] | ||||||||||
15h | SEQ2A_STEP5_DATA | 0000h | SEQ2A_STEP5_DAT[15:0] | |||||||
SEQ2A_STEP5_DAT[15:0] | ||||||||||
16h | SEQ2A_STEP6_DATA | 0000h | SEQ2A_STEP6_DAT[15:0] | |||||||
SEQ2A_STEP6_DAT[15:0] | ||||||||||
17h | SEQ2A_STEP7_DATA | 0000h | SEQ2A_STEP7_DAT[15:0] | |||||||
SEQ2A_STEP7_DAT[15:0] | ||||||||||
18h | SEQ2A_STEP8_DATA | 0000h | SEQ2A_STEP8_DAT[15:0] | |||||||
SEQ2A_STEP8_DAT[15:0] | ||||||||||
19h | SEQ2A_STEP9_DATA | 0000h | SEQ2A_STEP9_DAT[15:0] | |||||||
SEQ2A_STEP9_DAT[15:0] | ||||||||||
1Ah | SEQ2A_STEP10_DATA | 0000h | SEQ2A_STEP10_DAT[15:0] | |||||||
SEQ2A_STEP10_DAT[15:0] | ||||||||||
1Bh | SEQ2A_STEP11_DATA | 0000h | SEQ2A_STEP11_DAT[15:0] | |||||||
SEQ2A_STEP11_DAT[15:0] | ||||||||||
1Ch | SEQ2A_STEP12_DATA | 0000h | SEQ2A_STEP12_DAT[15:0] | |||||||
SEQ2A_STEP12_DAT[15:0] | ||||||||||
1Dh | SEQ2A_STEP13_DATA | 0000h | SEQ2A_STEP13_DAT[15:0] | |||||||
SEQ2A_STEP13_DAT[15:0] | ||||||||||
1Eh | SEQ2A_STEP14_DATA | 0000h | SEQ2A_STEP14_DAT[15:0] | |||||||
SEQ2A_STEP14_DAT[15:0] | ||||||||||
1Fh | SEQ2A_STEP15_DATA | 0000h | SEQ2A_STEP15_DAT[15:0] | |||||||
SEQ2A_STEP15_DAT[15:0] | ||||||||||
SECTION 1 | ||||||||||
40h | DEVICE_MONITOR_CFG | 0000h | REG_MAP1_CRC_EN | CRC_TYPE | SCLK_COUNTER_EN | TIMEOUT_EN | RESERVED | FAULT_POL | ||
RESERVED | MHD_POL | MHD_CFG[1:0] | ||||||||
41h | SUPPLY_MONITOR_CFG1 | 0000h | AVDD_OV_EN | AVDD_UV_EN | IOVDD_OV_EN | IOVDD_UV_EN | DVDD_OV_EN | DVDD_UV_EN | AVDD_OSC_EN | IOVDD_OSC_EN |
DVDD_OSC_EN | AVDD_OTW_EN | IOVDD_OTW_EN | AVDD_CL_EN | IOVDD_CL_EN | AGNDA_DISC_EN | AGNDB_DISC_EN | DGND_DISC_EN | |||
42h | SUPPLY_MONITOR_CFG2 | 10F0h | RESERVED | IOVDD_OV_TH | IOVDD_UV_TH | RESERVED | ||||
AVDD_OTW_CFG[1:0] | IOVDD_OTW_CFG[1:0] | RESERVED | ||||||||
43h | CLOCK_MONITOR_CFG | 0000h | RESERVED | |||||||
RESERVED | MCLK_MON_EN | OSCD_WD_EN | MCLK_WD_EN | |||||||
44h | SUPPLY_MONITOR_DIAGNOSTIC_CFG | 0000h | AVDD_OV_DIAG_EN | AVDD_UV_DIAG_EN | IOVDD_OV_DIAG_EN | IOVDD_UV_DIAG_EN | DVDD_OV_DIAG_EN | DVDD_UV_DIAG_EN | AVDD_OSC_DIAG_EN | IOVDD_OSC_DIAG_EN |
DVDD_OSC_DIAG_EN | RESERVED | AGNDA_DISC_DIAG_EN | AGNDB_DISC_DIAG_EN | DGND_DISC_DIAG_EN | ||||||
45h | CLOCK_MONITOR_DIAGNOSTIC_CFG | 0000h | SPARE[11:0] | |||||||
SPARE[11:0] | MCLK_HI_DIAG_EN | MCLK_LO_DIAG_EN | OSCD_WD_DIAG_EN | MCLK_WD_DIAG_EN | ||||||
46h | DIGITAL_MONITOR_DIAGNOSTIC_CFG | 0000h | RESERVED | MEM_MAP_CRC_DIAG[1:0] | ||||||
RESERVED | GPIOA_DIAG_EN | GPIOB_DIAG_EN | GPIO_DIAG_EN | |||||||
47h | SUPPLY_FAULT_MASK | 0000h | AVDD_OV_MASK | AVDD_UV_MASK | IOVDD_OV_MASK | IOVDD_UV_MASK | DVDD_OV_MASK | DVDD_UV_MASK | AVDD_OSC_MASK | IOVDD_OSC_MASK |
DVDD_OSC_MASK | AVDD_OTW_MASK | IOVDD_OTW_MASK | AVDD_CL_MASK | IOVDD_CL_MASK | AGNDA_DISC_MASK | AGNDB_DISC_MASK | DGND_DISC_MASK | |||
48h | CLOCK_FAULT_MASK | 0000h | RESERVED | |||||||
RESERVED | MCLK_FAULT_MASK | OSCD_WD_MASK | MCLK_WD_MASK | |||||||
49h | DIGITAL_FAULT_MASK | 0000h | REG_MAP1_CRC_FAULT_MASK | REG_MAP2_CRC_FAULT_MASK | REG_MAP3_CRC_FAULT_MASK | RESERVED | MEM_MAP_CRC_FAULT_MASK | RESERVED | ||
RESERVED | ||||||||||
4Ah | OCC_FAULT_MASK | 0000h | RESERVED | |||||||
RESERVED | OCCA_HT_MASK | OCCA_LT_MASK | OCCB_HT_MASK | OCCB_LT_MASK | ||||||
4Bh | FAULT_PIN_MASK | 0780h | RESERVED | SUPPLY_FAULT_MASK | CLOCK_FAULT_MASK | DIGITAL_FAULT_MASK | OCC_FAULT_MASK | SPI_CRC_FAULT_MASK | SPI_TIMEOUT_MASK | SCLK_COUNT_FAULT_MASK |
REG_ACCESS_FAULT_MASK | RESERVED | |||||||||
4Ch | DEVICE_CFG | 0000h | RESERVED | DRDY_CTRL | RESERVED | CLK_SOURCE | WORD_LENGTH | RESERVED | OP_MODE[1:0] | |
RESERVED | ||||||||||
4Dh | GPIO_CFG | 0000h | RESERVED | GPIO4_FMT | GPIO3_FMT | GPIO2_FMT | GPIO1_FMT | GPIO0_FMT | GPIO4_DIR | GPIO3_DIR |
GPIO2_DIR | GPIO1_DIR | GPIO0_DIR | GPIO4_SRC | GPIO3_SRC | GPIO2_SRC | RESERVED | GPIO0_SRC | |||
4Eh | GPO_DATA | 0000h | SPARE[10:0] | |||||||
SPARE[10:0] | GPO4_DAT | GPO3_DAT | GPO2_DAT | GPO1_DAT | GPO0_DAT | |||||
4Fh | GPIO0_LL_PWM_CFG | 007Fh | GPIO0_PWM_TB[1:0] | GPIO0_LL_PWM_HC[6:0] | ||||||
GPIO0_LL_PWM_HC[6:0] | GPIO0_LL_PWM_LC[6:0] | |||||||||
50h | GPIO0_LH_PWM_CFG | 3F80h | RESERVED | GPIO0_LH_PWM_HC[6:0] | ||||||
GPIO0_LH_PWM_HC[6:0] | GPIO0_LH_PWM_LC[6:0] | |||||||||
51h | GPIO1_LL_PWM_CFG | 007Fh | GPIO1_PWM_TB[1:0] | GPIO1_LL_PWM_HC[6:0] | ||||||
GPIO1_LL_PWM_HC[6:0] | GPIO1_LL_PWM_LC[6:0] | |||||||||
52h | GPIO1_LH_PWM_CFG | 3F80h | RESERVED | GPIO1_LH_PWM_HC[6:0] | ||||||
GPIO1_LH_PWM_HC[6:0] | GPIO1_LH_PWM_LC[6:0] | |||||||||
53h | GPIO2_LL_PWM_CFG | 007Fh | GPIO2_PWM_TB[1:0] | GPIO2_LL_PWM_HC[6:0] | ||||||
GPIO2_LL_PWM_HC[6:0] | GPIO2_LL_PWM_LC[6:0] | |||||||||
54h | GPIO2_LH_PWM_CFG | 3F80h | RESERVED | GPIO2_LH_PWM_HC[6:0] | ||||||
GPIO2_LH_PWM_HC[6:0] | GPIO2_LH_PWM_LC[6:0] | |||||||||
55h | GPIO3_LL_PWM_CFG | 007Fh | GPIO3_PWM_TB[1:0] | GPIO3_LL_PWM_HC[6:0] | ||||||
GPIO3_LL_PWM_HC[6:0] | GPIO3_LL_PWM_LC[6:0] | |||||||||
56h | GPIO3_LH_PWM_CFG | 3F80h | RESERVED | GPIO3_LH_PWM_HC[6:0] | ||||||
GPIO3_LH_PWM_HC[6:0] | GPIO3_LH_PWM_LC[6:0] | |||||||||
57h | GPIO4_LL_PWM_CFG | 007Fh | GPIO4_PWM_TB[1:0] | GPIO4_LL_PWM_HC[6:0] | ||||||
GPIO4_LL_PWM_HC[6:0] | GPIO4_LL_PWM_LC[6:0] | |||||||||
58h | GPIO4_LH_PWM_CFG | 3F80h | RESERVED | GPIO4_LH_PWM_HC[6:0] | ||||||
GPIO4_LH_PWM_HC[6:0] | GPIO4_LH_PWM_LC[6:0] | |||||||||
59h | SPARE_59h | 5555h | SPARE[15:0] | |||||||
SPARE[15:0] | ||||||||||
7Eh | REGISTER_MAP1_CRC | 0000h | REG_MAP1_CRC_VALUE[15:0] | |||||||
REG_MAP1_CRC_VALUE[15:0] | ||||||||||
SECTION 2 | ||||||||||
80h | REGMAP2_TDACA_CFG | 0000h | REG_MAP2_CRC_EN | RESERVED | ||||||
RESERVED | TDACA_VALUE[2:0] | |||||||||
81h | GPIOA_CFG | 8000h | RESERVED | SPARE[2:0] | GPIO1A_FMT | GPIO0A_FMT | GPIO1A_DIR | GPIO0A_DIR | ||
GPIO1A_PWM_TB[1:0] | GPIO0A_PWM_TB[1:0] | SPARE[1:0] | GPO1A_DAT | GPO0A_DAT | ||||||
82h | ADC1A_CFG1 | 0400h | RESERVED | CONV_MODE1A | OSR1A[2:0] | |||||
RESERVED | GC1A_EN | GC1A_DELAY[2:0] | ||||||||
83h | ADC1A_CFG2 | 8010h | ADC1A_EN | RESERVED | GAIN1A[1:0] | MUX1A[1:0] | ||||
RESERVED | OWD1A_SOURCE_MUX | OWD1A_SINK_MUX | OWD1A_SOURCE_VALUE[1:0] | OWD1A_SINK_VALUE[1:0] | ||||||
84h | ADC1A_OCAL_MSB | 0000h | OCAL1A[23:8] | |||||||
OCAL1A[23:8] | ||||||||||
85h | ADC1A_OCAL_LSB | 0000h | OCAL1A[7:0] | |||||||
RESERVED | ||||||||||
86h | ADC1A_GCAL | 0000h | GCAL1A[15:0] | |||||||
GCAL1A[15:0] | ||||||||||
87h | OCCA_CFG | 0000h | OCCA_EN | OCCA_POL | RESERVED | OCCA_NUM[4:0] | ||||
RESERVED | ||||||||||
88h | OCCA_HIGH_THRESHOLD | 7FFFh | OCCA_HIGH_TH[15:0] | |||||||
OCCA_HIGH_TH[15:0] | ||||||||||
89h | OCCA_LOW_THRESHOLD | 8000h | OCCA_LOW_TH[15:0] | |||||||
OCCA_LOW_TH[15:0] | ||||||||||
8Ah | SPARE_8Ah | 5555h | SPARE[15:0] | |||||||
SPARE[15:0] | ||||||||||
8Bh | ADC2A_CFG1 | 8010h | ADC2A_EN | RESERVED | VCMA_EN | OWD2A_SOURCE_MUX[2:0] | ||||
OWD2A_SOURCE_MUX[2:0] | OWD2A_SINK_MUX[2:0] | OWD2A_SOURCE_VALUE[1:0] | OWD2A_SINK_VALUE[1:0] | |||||||
8Ch | ADC2A_CFG2 | 0000h | SEQ2A_MODE[1:0] | RESERVED | MUX2A_DELAY[2:0] | |||||
RESERVED | OSR2A[1:0] | |||||||||
8Dh | SPARE_8Dh | 0000h | RESERVED | |||||||
SPARE[7:0] | ||||||||||
8Eh | ADC2A_OCAL | 0000h | OCAL2A[15:0] | |||||||
OCAL2A[15:0] | ||||||||||
8Fh | ADC2A_GCAL | 0000h | GCAL2A[15:0] | |||||||
GCAL2A[15:0] | ||||||||||
90h | SEQ2A_STEP0_CFG | 0000h | SEQ2A_STEP0_EN | SEQ2A_STEP0_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP0_CH_N | SEQ2A_STEP0_CH_P[3:0] | ||||||||
91h | SEQ2A_STEP1_CFG | 0001h | SEQ2A_STEP1_EN | SEQ2A_STEP1_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP1_CH_N | SEQ2A_STEP1_CH_P[3:0] | ||||||||
92h | SEQ2A_STEP2_CFG | 0002h | SEQ2A_STEP2_EN | SEQ2A_STEP2_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP2_CH_N | SEQ2A_STEP2_CH_P[3:0] | ||||||||
93h | SEQ2A_STEP3_CFG | 0003h | SEQ2A_STEP3_EN | SEQ2A_STEP3_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP3_CH_N | SEQ2A_STEP3_CH_P[3:0] | ||||||||
94h | SEQ2A_STEP4_CFG | 0004h | SEQ2A_STEP4_EN | SEQ2A_STEP4_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP4_CH_N | SEQ2A_STEP4_CH_P[3:0] | ||||||||
95h | SEQ2A_STEP5_CFG | 0005h | SEQ2A_STEP5_EN | SEQ2A_STEP5_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP5_CH_N | SEQ2A_STEP5_CH_P[3:0] | ||||||||
96h | SEQ2A_STEP6_CFG | 0006h | SEQ2A_STEP6_EN | SEQ2A_STEP6_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP6_CH_N | SEQ2A_STEP6_CH_P[3:0] | ||||||||
97h | SEQ2A_STEP7_CFG | 0007h | SEQ2A_STEP7_EN | SEQ2A_STEP7_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP7_CH_N | SEQ2A_STEP7_CH_P[3:0] | ||||||||
98h | SEQ2A_STEP8_CFG | 0008h | SEQ2A_STEP8_EN | SEQ2A_STEP8_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP8_CH_N | SEQ2A_STEP8_CH_P[3:0] | ||||||||
99h | SEQ2A_STEP9_CFG | 0009h | SEQ2A_STEP9_EN | SEQ2A_STEP9_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP9_CH_N | SEQ2A_STEP9_CH_P[3:0] | ||||||||
9Ah | SEQ2A_STEP10_CFG | 000Ah | SEQ2A_STEP10_EN | SEQ2A_STEP10_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP10_CH_N | SEQ2A_STEP10_CH_P[3:0] | ||||||||
9Bh | SEQ2A_STEP11_CFG | 000Bh | SEQ2A_STEP11_EN | SEQ2A_STEP11_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP11_CH_N | SEQ2A_STEP11_CH_P[3:0] | ||||||||
9Ch | SEQ2A_STEP12_CFG | 000Ch | SEQ2A_STEP12_EN | SEQ2A_STEP12_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP12_CH_N | SEQ2A_STEP12_CH_P[3:0] | ||||||||
9Dh | SEQ2A_STEP13_CFG | 000Dh | SEQ2A_STEP13_EN | SEQ2A_STEP13_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP13_CH_N | SEQ2A_STEP13_CH_P[3:0] | ||||||||
9Eh | SEQ2A_STEP14_CFG | 000Eh | SEQ2A_STEP14_EN | SEQ2A_STEP14_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP14_CH_N | SEQ2A_STEP14_CH_P[3:0] | ||||||||
9Fh | SEQ2A_STEP15_CFG | 000Fh | SEQ2A_STEP15_EN | SEQ2A_STEP15_GAIN[1:0] | RESERVED | |||||
RESERVED | SEQ2A_STEP15_CH_N | SEQ2A_STEP15_CH_P[3:0] | ||||||||
A0h | SPARE_A0h | 0210h | RESERVED | SPARE[1:0] | RESERVED | |||||
RESERVED | SPARE[1:0] | RESERVED | ||||||||
A1h | SPARE_A1h | 0000h | SPARE[15:0] | |||||||
SPARE[15:0] | ||||||||||
A2h | SPARE_A2h | 0000h | SPARE[7:0] | |||||||
RESERVED | ||||||||||
A3h | SPARE_A3h | 0000h | SPARE[15:0] | |||||||
SPARE[15:0] | ||||||||||
BEh | REGISTER_MAP2_CRC | 0000h | REG_MAP2_CRC_VALUE[15:0] | |||||||
REG_MAP2_CRC_VALUE[15:0] | ||||||||||
SECTION 3 | ||||||||||
C0h | REGMAP3_TDACB_CFG | 0000h | REG_MAP3_CRC_EN | RESERVED | ||||||
RESERVED | TDACB_VALUE[2:0] | |||||||||
C1h | GPIOB_CFG | 8000h | RESERVED | SPARE[2:0] | GPIO1B_FMT | GPIO0B_FMT | GPIO1B_DIR | GPIO0B_DIR | ||
GPIO1B_PWM_TB[1:0] | GPIO0B_PWM_TB[1:0] | SPARE[1:0] | GPO1B_DAT | GPO0B_DAT | ||||||
C2h | ADC1B_CFG1 | 0400h | RESERVED | CONV_MODE1B | OSR1B[2:0] | |||||
RESERVED | GC1B_EN | GC1B_DELAY[2:0] | ||||||||
C3h | ADC1B_CFG2 | 8010h | ADC1B_EN | RESERVED | GAIN1B[1:0] | MUX1B[1:0] | ||||
RESERVED | OWD1B_SOURCE_MUX | OWD1B_SINK_MUX | OWD1B_SOURCE_VALUE[1:0] | OWD1B_SINK_VALUE[1:0] | ||||||
C4h | ADC1B_OCAL_MSB | 0000h | OCAL1B[23:8] | |||||||
OCAL1B[23:8] | ||||||||||
C5h | ADC1B_OCAL_LSB | 0000h | OCAL1B[7:0] | |||||||
RESERVED | ||||||||||
C6h | ADC1B_GCAL | 0000h | GCAL1B[15:0] | |||||||
GCAL1B[15:0] | ||||||||||
C7h | OCCB_CFG | 0000h | OCCB_EN | OCCB_POL | RESERVED | OCCB_NUM[4:0] | ||||
RESERVED | ||||||||||
C8h | OCCB_HIGH_THRESHOLD | 7FFFh | OCCB_HIGH_TH[15:0] | |||||||
OCCB_HIGH_TH[15:0] | ||||||||||
C9h | OCCB_LOW_THRESHOLD | 8000h | OCCB_LOW_TH[15:0] | |||||||
OCCB_LOW_TH[15:0] | ||||||||||
CAh | SPARE_CAh | 5555h | SPARE[15:0] | |||||||
SPARE[15:0] | ||||||||||
CBh | SPARE_CBh | 0010h | RESERVED | SPARE[6:0] | ||||||
SPARE[6:0] | RESERVED | |||||||||
CCh | SPARE_CCh | 0000h | SPARE[1:0] | RESERVED | SPARE[2:0] | |||||
RESERVED | SPARE[1:0] | |||||||||
CDh | SPARE_CDh | 0000h | RESERVED | |||||||
SPARE[7:0] | ||||||||||
CEh | SPARE_CEh | 0000h | SPARE[15:0] | |||||||
SPARE[15:0] | ||||||||||
CFh | SPARE_CFh | 0000h | SPARE[15:0] | |||||||
SPARE[15:0] | ||||||||||
D0h | SPARE_D0h | 0000h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
D1h | SPARE_D1h | 0001h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
D2h | SPARE_D2h | 0002h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
D3h | SPARE_D3h | 0003h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
D4h | SPARE_D4h | 0004h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
D5h | SPARE_D5h | 0005h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
D6h | SPARE_D6h | 0006h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
D7h | SPARE_D7h | 0007h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
D8h | SPARE_D8h | 0008h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
D9h | SPARE_D9h | 0009h | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
DAh | SPARE_DAh | 000Ah | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
DBh | SPARE_DBh | 000Bh | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
DCh | SPARE_DCh | 000Ch | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
DDh | SPARE_DDh | 000Dh | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
DEh | SPARE_DEh | 000Eh | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
DFh | SPARE_DFh | 000Fh | SPARE[2:0] | RESERVED | ||||||
RESERVED | SPARE[4:0] | |||||||||
E0h | SPARE_E0h | 0210h | RESERVED | SPARE[1:0] | RESERVED | |||||
RESERVED | SPARE[1:0] | RESERVED | ||||||||
E1h | SPARE_E1h | 0000h | SPARE[15:0] | |||||||
SPARE[15:0] | ||||||||||
E2h | SPARE_E2h | 0000h | SPARE[7:0] | |||||||
RESERVED | ||||||||||
E3h | SPARE_E3h | 0000h | SPARE[15:0] | |||||||
SPARE[15:0] | ||||||||||
FEh | REGISTER_MAP3_CRC | 0000h | REG_MAP3_CRC_VALUE[15:0] | |||||||
REG_MAP3_CRC_VALUE[15:0] |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REV[7:0] | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC_COUNT[2:0] | DEVICE_ID[4:0] | ||||||
R-011b | R-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | REV[7:0] | R | X | Revision ID Values are subject to change without notice |
7:5 | ADC_COUNT[2:0] | R | 011b | ADC count 011b = 3 (ADC1A, ADC1B, ADC2A) |
4:0 | DEVICE_ID[4:0] | R | X | Device ID Values are subject to change without notice |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESETn | SUPPLY_FAULTn | CLOCK_FAULTn | DIGITAL_FAULTn | OCC_FAULTn | SPI_CRC_FAULTn | SPI_TIMEOUTn | SCLK_COUNT_FAULTn |
R/W-0b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R-1b | R-1b | R-1b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_ACCESS_FAULTn | COMMAND_RESPONSE[3:0] | LOCK | CLOCK | MODE | |||
R-1b | R-1001b | R-0b | R-0b | R-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESETn | R/W | 0b | RESET flag Indicates a device reset occurred. Write 1b to clear this bit to 1b. 0b = Reset occurred 1b = No reset occurred |
14 | SUPPLY_FAULTn | R/W | 1b | Supply fault flag Indicates that one or more of the unmasked supply fault flags in the SUPPLY_STATUS register is set. Write 1b to clear this bit to 1b after all set unmasked supply fault flags are cleared. 0b = One or more of the unmasked supply fault flags is set 1b = None of the unmasked supply fault flags are set |
13 | CLOCK_FAULTn | R/W | 1b | Clock fault flag Indicates that one or more of the unmasked clock fault flags in the CLOCK_STATUS register is set. Write 1b to clear this bit to 1b after all set unmasked clock fault flags are cleared. 0b = One or more of the unmasked clock fault flags is set 1b = None of the unmasked supply clock fault flags are set |
12 | DIGITAL_FAULTn | R/W | 1b | Digital fault flag Indicates that one or more of the unmasked digital fault flags in the DIGITAL_STATUS register is set. Write 1b to clear this bit to 1b after all set unmasked digital fault flags are cleared. 0b = One or more of the unmasked digital fault flags is set 1b = None of the unmasked digital fault flags are set |
11 | OCC_FAULTn | R/W | 1b | Overcurrent comparator fault flag Indicates that one or more of the unmasked overcurrent comparator fault flags in the OCC_STATUS register is set. Write 1b to clear this bit to 1b after all set unmasked overcurrent comparator fault flags are cleared. 0b = One or more of the unmasked overcurrent comparator fault flags is set 1b = None of the unmasked overcurrent comparator fault flags are set |
10 | SPI_CRC_FAULTn | R | 1b | SPI CRC fault flag Indicates an SPI CRC fault occurred in the previous SPI frame. This bit clears automatically to 1b in each new SPI frame. 0b = SPI CRC fault occurred 1b = No SPI CRC fault occurred |
9 | SPI_TIMEOUTn | R | 1b | SPI timeout fault flag Indicates an SPI timeout fault occurred in the previous SPI frame. This bit clears automatically to 1b in each new SPI frame. 0b = SPI timeout fault occurred 1b = No SPI timeout fault occurred |
8 | SCLK_COUNT_FAULTn | R | 1b | SCLK counter fault flag Indicates an SCLK counter fault occurred in the previous SPI frame (that is, fewer or more SCLKs than required for the previous frame were sent). This bit clears automatically to 1b in each new SPI frame. 0b = SCLK counter fault occurred 1b = No SCLK counter fault occurred |
7 | REG_ACCESS_FAULTn | R | 1b | Register access fault flag Indicates a read or write access to an invalid register address (register address FFh or beyond) occurred. This flag sets to 0b in the subsequent frame following the frame where a read or write operation to a register with an invalid register address was attempted. This bit clears automatically to 1b in each new SPI frame. 0b = Register access fault occurred 1b = No register access fault occurred |
6:3 | COMMAND_RESPONSE[3:0] | R | 1001b | Command response indication Indicates which command was executed in the previous SPI frame. 0000b = Invalid response that does not occur under normal circumstances. Can indicate a stuck-at SDO signal or that the device is held in reset. 0001b = NULL command 0010b = LOCK command 0011b = UNLOCK command 0100b = RREG command 0101b = NULL command (because a NULL command was correctly sent as the second frame after a RREG command). This response serves as the frame counter for the two-frame RREG command. 0110b = WREG command 0111b = Invalid response that does not occur under normal circumstances. 1000b = Invalid response that does not occur under normal circumstances. 1001b = NULL command (first frame after power-up or reset). This response is only sent in the first frame after reset or power-up, the second frame has the response based on the command sent in the first frame. 1010b = NULL command (resulting from one of the following errors: a timeout occurred before a complete command CRC was received, insufficient SCLKs were sent to complete a command, a CRC mismatch between the command word and command CRC word, or a CRC mismatch between data words and the data CRC word in a WREG command). For the NULL, RREG, LOCK, and UNLOCK commands, the command and command CRC words must be sent to complete the command. For the RESET command, the STATUS word, all ADC data words, and the output CRC word must be read to complete the command. For the WREG command, the command and command CRC words, as well as the data and data CRC words must be sent to complete the command. 1011b = NULL command (resulting from an invalid command word with a matching CRC between the command word and command CRC word). 1100b = NULL command (resulting from a command other than the NULL command was sent in the second frame after the RREG command and ignored). This response serves as the frame counter for the two-frame RREG command. 1101b = NULL command (the RESET or WREG commands are ignored because the device is locked). 1110b = Invalid response that does not occur under normal circumstances. 1111b = Invalid response that does not occur under normal circumstances. Can indicate a stuck-at SDO signal. |
2 | LOCK | R | 0b | Lock state indication Indicates if the device is locked or unlocked. 0b = Device is unlocked 1b = Device is locked |
1 | CLOCK | R | 0b | Clock source indication Indicates which clock source the device is currently using. 0b = Internal oscillator 1b = External clock |
0 | MODE | R | 0b | Operating mode indication Indicates which operating mode the device is currently in. 0b = Active mode 1b = Standby or power-down mode |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_COUNT[1:0] | RESERVED | CONV1A_COUNT[1:0] | CONV1B_COUNT[1:0] | ||||
R-00b | R-00b | R-00b | R-00b | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_ACTIVE | RESERVED | |||||
R-000000b | R-0b | R-0b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | SEQ2A_COUNT[1:0] | R | 00b | ADC2A sequence counter Circular counter that increments each time a new sequence on ADC2A completes. This counter resets to 00b when ADC2A is disabled, when the device is put in standby or power-down mode, or after a device reset. |
13:12 | RESERVED | R | 00b | Reserved Always reads 00b. |
11:10 | CONV1A_COUNT[1:0] | R | 00b | ADC1A conversion counter Circular counter that increments each time a new conversion on ADC1A completes. This counter resets to 00b when ADC1A is disabled, when the device is put in standby or power-down mode, or after a device reset. |
9:8 | CONV1B_COUNT[1:0] | R | 00b | ADC1B conversion counter Circular counter that increments each time a new conversion on ADC1B completes. This counter resets to 00b when ADC1B is disabled, when the device is put in standby or power-down mode, or after a device reset. |
7:2 | RESERVED | R | 000000b | Reserved Always reads 000000b. |
1 | SEQ2A_ACTIVE | R | 0b | ADC2A sequence in progress indication Indicates that a sequence on ADC2A is currently in progress. Changes to registers from address 8Ch to 9Fh of ADC2A must only be made when ADC2A is disabled. 0b = No sequence in progress 1b = Sequence in progress |
0 | RESERVED | R | 0b | Reserved Always reads 0b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
AVDD_OVn | AVDD_UVn | IOVDD_OVn | IOVDD_UVn | DVDD_OVn | DVDD_UVn | AVDD_OSCn | IOVDD_OSCn |
R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DVDD_OSCn | AVDD_OTWn | IOVDD_OTWn | AVDD_CLn | IOVDD_CLn | AGNDA_DISCn | AGNDB_DISCn | DGND_DISCn |
R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | R/W-1b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | AVDD_OVn | R/W | 1b | AVDD overvoltage fault flag Indicates the AVDD supply voltage exceeded the AVDD overvoltage threshold. See the AVDD monitor description for details regarding the AVDD LDO shutdown during overvoltage. Write 1b to clear this bit to 1b. 0b = Overvoltage fault occurred 1b = No overvoltage fault occurred |
14 | AVDD_UVn | R/W | 1b | AVDD undervoltage fault flag Indicates the AVDD supply voltage dropped below the AVDD undervoltage threshold. Write 1b to clear this bit to 1b. 0b = Undervoltage fault occurred 1b = No undervoltage fault occurred |
13 | IOVDD_OVn | R/W | 1b | IOVDD overvoltage fault flag Indicates the IOVDD supply voltage exceeded the IOVDD overvoltage threshold. See the IOVDD monitor description for details regarding the IOVDD LDO shutdown during overvoltage. Write 1b to clear this bit to 1b. 0b = Overvoltage fault occurred 1b = No overvoltage fault occurred |
12 | IOVDD_UVn | R/W | 1b | IOVDD undervoltage fault flag Indicates the IOVDD supply voltage dropped below the IOVDD undervoltage threshold. Write 1b to clear this bit to 1b. 0b = Undervoltage fault occurred 1b = No undervoltage fault occurred |
11 | DVDD_OVn | R/W | 1b | DVDD overvoltage fault flag Indicates the DVDD supply voltage exceeded the DVDD overvoltage threshold. See the DVDD monitor description for details regarding the DVDD LDO shutdown during overvoltage. Write 1b to clear this bit to 1b. 0b = Overvoltage fault occurred 1b = No overvoltage fault occurred |
10 | DVDD_UVn | R/W | 1b | DVDD undervoltage fault flag Indicates the DVDD supply voltage dropped below the DVDD undervoltage threshold. Write 1b to clear this bit to 1b. 0b = Undervoltage fault occurred 1b = No undervoltage fault occurred |
9 | AVDD_OSCn | R/W | 1b | AVDD oscillation fault flag Indicates the AVDD supply voltage is oscillating. Write 1b to clear this bit to 1b. 0b = Oscillation fault occurred 1b = No oscillation fault occurred |
8 | IOVDD_OSCn | R/W | 1b | IOVDD oscillation fault flag Indicates the IOVDD supply voltage is oscillating. Write 1b to clear this bit to 1b. 0b = Oscillation fault occurred 1b = No oscillation fault occurred |
7 | DVDD_OSCn | R/W | 1b | DVDD oscillation fault flag Indicates the DVDD supply voltage is oscillating. Write 1b to clear this bit to 1b. 0b = Oscillation fault occurred 1b = No oscillation fault occurred |
6 | AVDD_OTWn | R/W | 1b | AVDD overtemperature warning flag Indicates the AVDD LDO temperature exceeded the AVDD overtemperature warning threshold. Write 1b to clear this bit to 1b. 0b = Overtemperature warning 1b = No overtemperature warning |
5 | IOVDD_OTWn | R/W | 1b | IOVDD overtemperature warning flag Indicates the IOVDD LDO temperature exceeded the IOVDD overtemperature warning threshold. Write 1b to clear this bit to 1b. 0b = Overtemperature warning 1b = No overtemperature warning |
4 | AVDD_CLn | R/W | 1b | AVDD current limit flag Indicates the AVDD LDO current limit is active. Write 1b to clear this bit to 1b. 0b = Current limit 1b = No current limit |
3 | IOVDD_CLn | R/W | 1b | IOVDD current limit flag Indicates the IOVDD LDO current limit is active. Write 1b to clear this bit to 1b. 0b = Current limit 1b = No current limit |
2 | AGNDA_DISCn | R/W | 1b | AGNDA pin disconnect detection flag Indicates the AGNDA pin is disconnected. Write 1b to clear this bit to 1b. 0b = AGNDA pin disconnected 1b = AGNDA pin connected |
1 | AGNDB_DISCn | R/W | 1b | AGNDB pin disconnect detection flag Indicates the AGNDB pin is disconnected. Write 1b to clear this bit to 1b. 0b = AGNDB pin disconnected 1b = AGNDB pin connected |
0 | DGND_DISCn | R/W | 1b | DGND pin disconnect detection flag Indicates the DGND pin is disconnected. Write 1b to clear this bit to 1b. 0b = DGND pin disconnected 1b = DGND pin connected |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-1111110000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MCLK_FAULTn | OSCD_WDn | MCLK_WDn | ||||
R-1111110000000b | R/W-1b | R/W-1b | R/W-1b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:3 | RESERVED | R | 1111110000000b | Reserved Always reads 1111110000000b. |
2 | MCLK_FAULTn | R/W | 1b | MCLK frequency too high or too low fault flag Indicates the main clock frequency of the selected clock source either exceeded the clock frequency high threshold or dropped below the clock frequency low threshold. Write 1b to clear this bit to 1b. 0b = MCLK frequency too high or too low fault occurred 1b = No MCLK frequency too high or too low fault occurred |
1 | OSCD_WDn | R/W | 1b | Diagnostic oscillator watchdog fault flag Indicates a diagnostic oscillator watchdog fault occurred. Write 1b to clear this bit to 1b. 0b = Watchdog fault occurred 1b = No watchdog fault occurred |
0 | MCLK_WDn | R/W | 1b | Main clock watchdog fault flag Indicates a main clock watchdog fault occurred. Write 1b to clear this bit to 1b. 0b = Watchdog fault occurred 1b = No watchdog fault occurred |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_MAP1_CRC_FAULTn | REG_MAP2_CRC_FAULTn | REG_MAP3_CRC_FAULTn | RESERVED | MEM_MAP_CRC_FAULTn | OTP_BANK | RESERVED | |
R/W-1b | R/W-1b | R/W-1b | R-0b | R/W-1b | R-1b | R-0000000000b | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | REG_MAP1_CRC_FAULTn | R/W | 1b | Register map section 1 CRC fault flag Indicates a register map CRC fault in section 1 (register address space from 40h to 59h) occurred. Write 1b to clear this bit to 1b. 0b = Register map CRC fault occurred 1b = No register map CRC fault occurred |
14 | REG_MAP2_CRC_FAULTn | R/W | 1b | Register map section 2 CRC fault flag Indicates a register map CRC fault in section 2 (register address space from 80h to A3h) occurred. Write 1b to clear this bit to 1b. 0b = Register map CRC fault occurred 1b = No register map CRC fault occurred |
13 | REG_MAP3_CRC_FAULTn | R/W | 1b | Register map section 3 CRC fault flag Indicates a register map CRC fault in section 3 (register address space from C0h to E3h) occurred. Write 1b to clear this bit to 1b. 0b = Register map CRC fault occurred 1b = No register map CRC fault occurred |
12 | RESERVED | R | 0b | Reserved Always reads 0b. |
11 | MEM_MAP_CRC_FAULTn | R/W | 1b | Memory map CRC fault flag Indicates a memory map CRC fault in the internal memory occurred. Write 1b to clear this bit to 1b. Reset the device in case the flag continues to set to 0b. 0b = Memory map CRC fault occurred 1b = No memory map CRC fault occurred |
10 | OTP_BANK | R | 1b | OTP bank indication Indicates which OTP bank the device selected after reset. The OTP_BANK bit does not trigger the DIGITAL_FAULTn bit in the STATUS_MSB register. Reset the device in case the flag indicates that the backup OTP bank is used. 0b = Backup OTP bank (bank 1) 1b = Primary OTP bank (bank 0) |
9:0 | RESERVED | R | 0000000000b | Reserved Always reads 0000000000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OCCA_HTn | OCCA_LTn | OCCB_HTn | OCCB_LTn | |||
R-000000000000b | R/W-1b | R/W-1b | R/W-1b | R/W-1b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:4 | RESERVED | R | 000000000000b | Reserved Always reads 000000000000b. |
3 | OCCA_HTn | R/W | 1b | ADC1A overcurrent comparator high threshold fault flag Indicates the ADC1A digital fast filter output exceeded the set high threshold for the set amount of conversions. Write 1b to clear this bit to 1b. 0b = High threshold fault occurred 1b = No high threshold fault occurred |
2 | OCCA_LTn | R/W | 1b | ADC1A overcurrent comparator low threshold fault flag Indicates the ADC1A digital fast filter output dropped below the set low threshold for the set amount of conversions. Write 1b to clear this bit to 1b. 0b = Low threshold fault occurred 1b = No low threshold fault occurred |
1 | OCCB_HTn | R/W | 1b | ADC1B overcurrent comparator high threshold fault flag Indicates the ADC1B digital fast filter output exceeded the set high threshold for the set amount of conversions. Write 1b to clear this bit to 1b. 0b = High threshold fault occurred 1b = No high threshold fault occurred |
0 | OCCB_LTn | R/W | 1b | ADC1B overcurrent comparator low threshold fault flag Indicates the ADC1B digital fast filter output dropped below the set low threshold for the set amount of conversions. Write 1b to clear this bit to 1b. 0b = Low threshold fault occurred 1b = No low threshold fault occurred |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPI4_DAT[1:0] | ||||||
R-000000b | R-00b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPI3_DAT[1:0] | GPI2_DAT[1:0] | GPI1_DAT[1:0] | GPI0_DAT[1:0] | ||||
R-00b | R-00b | R-00b | R-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:10 | RESERVED | R | 000000b | Reserved Always reads 000000b. |
9:8 | GPI4_DAT[1:0] | R | 00b | GPIO4 data readback Readback value of GPIO4 when configured as a digital input or output. 00b = Low (static low or PWM with a low period >66.6%) 01b = Weak low (PWM with a low period ≥50% but ≤66.6%) 10b = Weak high (PWM with a high period >50% but ≤66.6%) 11b = High (static high or PWM with a high period >66.6%) |
7:6 | GPI3_DAT[1:0] | R | 00b | GPIO3 data readback Readback value of GPIO3 when configured as a digital input or output. 00b = Low (static low or PWM with a low period >66.6%) 01b = Weak low (PWM with a low period ≥50% but ≤66.6%) 10b = Weak high (PWM with a high period >50% but ≤66.6%) 11b = High (static high or PWM with a high period >66.6%) |
5:4 | GPI2_DAT[1:0] | R | 00b | GPIO2 data readback Readback value of GPIO2 when configured as a digital input or output. 00b = Low (static low or PWM with a low period >66.6%) 01b = Weak low (PWM with a low period ≥50% but ≤66.6%) 10b = Weak high (PWM with a high period >50% but ≤66.6%) 11b = High (static high or PWM with a high period >66.6%) |
3:2 | GPI1_DAT[1:0] | R | 00b | GPIO1 data readback Readback value of GPIO1 when configured as a digital input or output. 00b = Low (static low or PWM with a low period >66.6%) 01b = Weak low (PWM with a low period ≥50% but ≤66.6%) 10b = Weak high (PWM with a high period >50% but ≤66.6%) 11b = High (static high or PWM with a high period >66.6%) |
1:0 | GPI0_DAT[1:0] | R | 00b | GPIO0 data readback Readback value of GPIO0 when configured as a digital input or output. 00b = Low (static low or PWM with a low period >66.6%) 01b = Weak low (PWM with a low period ≥50% but ≤66.6%) 10b = Weak high (PWM with a high period >50% but ≤66.6%) 11b = High (static high or PWM with a high period >66.6%) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPI1A_DAT[1:0] | GPI0A_DAT[1:0] | |||||
R-0000b | R-00b | R-00b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPI1B_DAT[1:0] | GPI0B_DAT[1:0] | |||||
R-0000b | R-00b | R-00b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
11:10 | GPI1A_DAT[1:0] | R | 00b | GPIO1A data readback Readback value of GPIO1A when configured as a digital input or output. 00b = Low (static low or PWM with a low period >66.6%) 01b = Weak low (PWM with a low period ≥50% but ≤66.6%) 10b = Weak high (PWM with a high period >50% but ≤66.6%) 11b = High (static high or PWM with a high period >66.6%) |
9:8 | GPI0A_DAT[1:0] | R | 00b | GPIO0A data readback Readback value of GPIO0A when configured as a digital input or output. 00b = Low (static low or PWM with a low period >66.6%) 01b = Weak low (PWM with a low period ≥50% but ≤66.6%) 10b = Weak high (PWM with a high period >50% but ≤66.6%) 11b = High (static high or PWM with a high period >66.6%) |
7:4 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
3:2 | GPI1B_DAT[1:0] | R | 00b | GPIO1B data readback Readback value of GPIO1B when configured as a digital input or output. 00b = Low (static low or PWM with a low period >66.6%) 01b = Weak low (PWM with a low period ≥50% but ≤66.6%) 10b = Weak high (PWM with a high period >50% but ≤66.6%) 11b = High (static high or PWM with a high period >66.6%) |
1:0 | GPI0B_DAT[1:0] | R | 00b | GPIO0B data readback Readback value of GPIO0B when configured as a digital input or output. 00b = Low (static low or PWM with a low period >66.6%) 01b = Weak low (PWM with a low period ≥50% but ≤66.6%) 10b = Weak high (PWM with a high period >50% but ≤66.6%) 11b = High (static high or PWM with a high period >66.6%) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | STARTA | RESERVED | STARTB | RESERVED | STOPA | RESERVED | STOPB |
R-0b | R/W-0b | R-0b | R/W-0b | R-0b | R/W-0b | R-0b | R/W-0b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_START | RESERVED | SEQ2A_STOP | RESERVED | |||
R-0b | R/W-0b | R-000b | R/W-0b | R-00b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0b | Reserved Always reads 0b. |
14 | STARTA | R/W | 0b | Start or re-start ADC1A conversions Write 1b to start or restart conversions of enabled ADC1A. Always reads back 0b. |
13 | RESERVED | R | 0b | Reserved Always reads 0b. |
12 | STARTB | R/W | 0b | Start or restart ADC1B conversions Write 1b to start or restart conversions of enabled ADC1B. Always reads back 0b. |
11 | RESERVED | R | 0b | Reserved Always reads 0b. |
10 | STOPA | R/W | 0b | Stop ADC1A conversions Write 1b to stop conversions of ADC1A in continuous-conversion mode. Ongoing conversions are allowed to complete. The STOPA bit has no effect in single-shot conversion mode. The STARTA bit takes priority over the STOPA bit if both bits are set during the same WREG command frame. The STOPA bit clears to 0b after the ongoing conversion finishes or when the STARTA bit is set before the ongoing conversion finishes, which aborts the ongoing conversion and restarts new conversions. |
9 | RESERVED | R | 0b | Reserved Always reads 0b. |
8 | STOPB | R/W | 0b | Stop ADC1B conversions Write 1b to stop conversions of ADC1B in continuous-conversion mode. Ongoing conversions are allowed to complete. The STOPB bit has no effect in single-shot conversion mode. The STARTB bit takes priority over the STOPB bit if both bits are set during the same WREG command frame. The STOPB bit clears to 0b after the ongoing conversion finishes or when the STARTB bit is set before the ongoing conversion finishes, which aborts the ongoing conversion and restarts new conversions. |
7 | RESERVED | R | 0b | Reserved Always reads 0b. |
6 | SEQ2A_START | R/W | 0b | Start ADC2A sequence Write 1b to start or restart sequence of ADC2A. Always reads back 0b. |
5:3 | RESERVED | R | 000b | Reserved Always reads 000b. |
2 | SEQ2A_STOP | R/W | 0b | Stop ADC2A sequence Write 1b to stop ADC2A sequence. A sequence in progress is allowed to finish. The SEQ2A_START bit takes priority over the SEQ2A_STOP bit if both bits are set during the same WREG command frame. The SEQ2A_STOP bit clears to 0b after the ongoing sequence finishes or when the SEQ2A_START bit is set before the ongoing sequence finishes, which aborts the ongoing sequence and restarts a new sequence. |
1:0 | RESERVED | R | 00b | Reserved Always reads 00b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP0_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP0_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP0_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 0 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP1_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP1_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP1_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 1 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP2_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP2_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP2_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 2 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP3_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP3_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP3_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 3 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP4_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP4_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP4_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 4 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP5_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP5_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP5_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 5 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP6_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP6_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP6_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 6 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP7_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP7_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP7_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 7 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP8_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP8_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP8_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 8 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP9_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP9_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP9_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 9 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP10_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP10_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP10_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 10 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP11_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP11_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP11_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 11 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP12_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP12_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP12_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 12 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP13_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP13_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP13_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 13 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP14_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP14_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP14_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 14 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP15_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQ2A_STEP15_DAT[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SEQ2A_STEP15_DAT[15:0] | R | 0000000000000000b | ADC2A sequence step 15 conversion data Value provided in two's complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_MAP1_CRC_EN | CRC_TYPE | SCLK_COUNTER_EN | TIMEOUT_EN | RESERVED | FAULT_POL | ||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-000b | R/W-0b | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MHD_POL | MHD_CFG[1:0] | |||||
R-00000b | R/W-0b | R/W-00b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | REG_MAP1_CRC_EN | R/W | 0b | Register map section 1 CRC enable Enables the register map CRC for section 1 (register address space from 40h to 59h). 0b = Disabled 1b = Enabled |
14 | CRC_TYPE | R/W | 0b | CRC type selection Selects the CRC polynomial that is used for the SPI and register map CRC calculation. 0b = 16-bit CCITT 1b = 16-bit ANSI |
13 | SCLK_COUNTER_EN | R/W | 0b | SCLK counter enable Enables the SCLK counter. 0b = Disabled 1b = Enabled |
12 | TIMEOUT_EN | R/W | 0b | SPI timeout enable Enables the SPI timeout. When enabled the timeout checks that a rising edge of CSn happens within 214 tOSCD cycles after a CSn falling edge. When a timeout occurs, the remainder of the SPI frame on SDI is ignored before the rising edge of CSn. A new SPI transaction starts at the next CSn falling edge. 0b = Disabled 1b = Enabled |
11:9 | RESERVED | R | 000b | Reserved Always reads back 000b. |
8 | FAULT_POL | R/W | 0b | FAULT pin polarity selection Selects the polarity of the FAULT pin. The actual output behavior of the GPIO2/FAULT pin, when configured as a FAULT output in the GPIO2_SRC bit, depends on the GPIO2_FMT setting. A FAULT is active when any of the non-masked STATUS_MSB[14:7] bits are active. 0b = Active low. In case of a fault a logic low level is driven. 1b = Active high. In case of a fault a logic high level is driven. |
7:3 | RESERVED | R | 00000b | Reserved Always reads back 00000b. |
2 | MHD_POL | R/W | 0b | Missing host detection fault pin polarity selection Selects the polarity of the MHD pin. The actual output behavior of the GPIO0/MHD pin, when configured as an MHD output in the GPIO0_SRC bit, depends on the GPIO0_FMT setting. 0b = Active low. In case of a fault a logic low level is driven. 1b = Active high. In case of a fault a logic high level is driven. |
1:0 | MHD_CFG[1:0] | R/W | 00b | Missing host detection configuration Detects when the host is not communicating with the device anymore. A watchdog timer checks the time between two valid commands with a valid CRC. If a valid command with a valid CRC is not received within the watchdog time window, the host is considered missing. When the watchdog times out, the GPIO0/MHD pin is set to active. To use the missing host detection mode, configure the GPIO0/MHD pin as an output using the GPIO0_DIR bit and the source for missing host detection mode using the GPIO0_SRC bit. To reset the GPIO0/MHD output after a missing host was detected, disable the missing host detection mode by setting MHD_CFG = 00b. 00b = Disabled 01b = 5120 x tOSCD (= 0.625 ms for fOSCD = 8.192 MHz) 10b = 10240 x tOSCD (= 1.25 ms for fOSCD = 8.192 MHz) 11b = 20480 x tOSCD (= 2.5 ms for fOSCD = 8.192 MHz) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
AVDD_OV_EN | AVDD_UV_EN | IOVDD_OV_EN | IOVDD_UV_EN | DVDD_OV_EN | DVDD_UV_EN | AVDD_OSC_EN | IOVDD_OSC_EN |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DVDD_OSC_EN | AVDD_OTW_EN | IOVDD_OTW_EN | AVDD_CL_EN | IOVDD_CL_EN | AGNDA_DISC_EN | AGNDB_DISC_EN | DGND_DISC_EN |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | AVDD_OV_EN | R/W | 0b | AVDD LDO overvoltage monitor enable Enables the AVDD LDO output overvoltage monitor. 0b = Disabled 1b = Enabled |
14 | AVDD_UV_EN | R/W | 0b | AVDD LDO undervoltage monitor enable Enables the AVDD LDO output undervoltage monitor. 0b = Disabled 1b = Enabled |
13 | IOVDD_OV_EN | R/W | 0b | IOVDD LDO overvoltage monitor enable Enables the IOVDD LDO output overvoltage monitor. 0b = Disabled 1b = Enabled |
12 | IOVDD_UV_EN | R/W | 0b | IOVDD LDO undervoltage monitor enable Enables the IOVDD LDO output undervoltage monitor. 0b = Disabled 1b = Enabled |
11 | DVDD_OV_EN | R/W | 0b | DVDD LDO overvoltage monitor enable Enables the DVDD LDO output overvoltage monitor. 0b = Disabled 1b = Enabled |
10 | DVDD_UV_EN | R/W | 0b | DVDD LDO undervoltage monitor enable Enables the DVDD LDO output undervoltage monitor. 0b = Disabled 1b = Enabled |
9 | AVDD_OSC_EN | R/W | 0b | AVDD LDO oscillation monitor enable Enables the AVDD LDO output oscillation monitor. 0b = Disabled 1b = Enabled |
8 | IOVDD_OSC_EN | R/W | 0b | IOVDD LDO oscillation monitor enable Enables the IOVDD LDO output oscillation monitor. 0b = Disabled 1b = Enabled |
7 | DVDD_OSC_EN | R/W | 0b | DVDD LDO oscillation monitor enable Enables the DVDD LDO output oscillation monitor. 0b = Disabled 1b = Enabled |
6 | AVDD_OTW_EN | R/W | 0b | AVDD LDO overtemperature warning monitor enable Enables the AVDD LDO overtemperature warning monitor. 0b = Disabled 1b = Enabled |
5 | IOVDD_OTW_EN | R/W | 0b | IOVDD LDO overtemperature warning monitor enable Enables the IOVDD LDO overtemperature warning monitor. 0b = Disabled 1b = Enabled |
4 | AVDD_CL_EN | R/W | 0b | AVDD LDO current limit enable Enables the AVDD LDO current limit. 0b = Disabled 1b = Enabled |
3 | IOVDD_CL_EN | R/W | 0b | IOVDD LDO current limit enable Enables the IOVDD LDO current limit. 0b = Disabled 1b = Enabled |
2 | AGNDA_DISC_EN | R/W | 0b | AGNDA disconnect monitor enable Enables the AGNDA disconnect monitor. 0b = Disabled 1b = Enabled |
1 | AGNDB_DISC_EN | R/W | 0b | AGNDB disconnect monitor enable Enables the AGNDB disconnect monitor. 0b = Disabled 1b = Enabled |
0 | DGND_DISC_EN | R/W | 0b | DGND disconnect monitor enable Enables the DGND disconnect monitor. 0b = Disabled 1b = Enabled |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | IOVDD_OV_TH | IOVDD_UV_TH | RESERVED | ||||
R-00b | R/W-0b | R/W-1b | R-0000b | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AVDD_OTW_CFG[1:0] | IOVDD_OTW_CFG[1:0] | RESERVED | |||||
R/W-11b | R/W-11b | R-0000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R | 00b | Reserved Always reads back 00b. |
13 | IOVDD_OV_TH | R/W | 0b | IOVDD overvoltage threshold selection Selects the threshold for the IOVDD LDO output overvoltage monitor. 0b = 5.7 V 1b = 3.9 V |
12 | IOVDD_UV_TH | R/W | 1b | IOVDD undervoltage threshold selection Selects the threshold for the IOVDD LDO output undervoltage monitor. 0b = 4.3 V 1b = 2.95 V |
11:8 | RESERVED | R | 0000b | Reserved Always reads back 0000b. |
7:6 | AVDD_OTW_CFG[1:0] | R/W | 11b | AVDD LDO overtemperature warning threshold selection Selects the threshold for AVDD LDO overtemperature warning. 00b = #dash<deg#C 01b = 100°C 10b = 120°C 11b = 140°C |
5:4 | IOVDD_OTW_CFG[1:0] | R/W | 11b | IOVDD LDO overtemperature warning threshold selection Selects the threshold for IOVDD LDO overtemperature warning. 00b = #dash<deg#C 01b = 100°C 10b = 120°C 11b = 140°C |
3:0 | RESERVED | R | 0000b | Reserved Always reads back 0000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | ||||||
R/W-000000b | R-0000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MCLK_MON_EN | OSCD_WD_EN | MCLK_WD_EN | ||||
R-0000000b | R/W-0b | R/W-0b | R/W-0b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:10 | RESERVED | R/W | 000000b | Reserved Always write 000000b. |
9:3 | RESERVED | R | 0000000b | Reserved Always reads back 0000000b. |
2 | MCLK_MON_EN | R/W | 0b | MCLK monitor enable Enables the main clock frequency monitor. 0b = Disabled 1b = Enabled |
1 | OSCD_WD_EN | R/W | 0b | Diagnostic oscillator watchdog enable Enables the diagnostic oscillator watchdog. 0b = Disabled 1b = Enabled |
0 | MCLK_WD_EN | R/W | 0b | Main clock watchdog enable Enables the main clock watchdog. 0b = Disabled 1b = Enabled |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
AVDD_OV_DIAG_EN | AVDD_UV_DIAG_EN | IOVDD_OV_DIAG_EN | IOVDD_UV_DIAG_EN | DVDD_OV_DIAG_EN | DVDD_UV_DIAG_EN | AVDD_OSC_DIAG_EN | IOVDD_OSC_DIAG_EN |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DVDD_OSC_DIAG_EN | RESERVED | AGNDA_DISC_DIAG_EN | AGNDB_DISC_DIAG_EN | DGND_DISC_DIAG_EN | |||
R/W-0b | R-0000b | R/W-0b | R/W-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | AVDD_OV_DIAG_EN | R/W | 0b | AVDD LDO overvoltage monitor diagnostic enable Enables the AVDD LDO output overvoltage monitor diagnostic. AVDD_OV_EN must be set for the diagnostic to work. The AVDD_OVn fault flag sets within tp(AVDD_OV) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
14 | AVDD_UV_DIAG_EN | R/W | 0b | AVDD LDO undervoltage monitor diagnostic enable Enables the AVDD LDO output undervoltage monitor diagnostic. AVDD_UV_EN must be set for the diagnostic to work. The AVDD_UVn fault flag sets within tp(AVDD_UV) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
13 | IOVDD_OV_DIAG_EN | R/W | 0b | IOVDD LDO overvoltage monitor diagnostic enable Enables the IOVDD LDO output overvoltage monitor diagnostic. IOVDD_OV_EN must be set for the diagnostic to work. The IOVDD_OVn fault flag sets within tp(IOVDD._OV) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
12 | IOVDD_UV_DIAG_EN | R/W | 0b | IOVDD LDO undervoltage monitor diagnostic enable Enables the IOVDD LDO output undervoltage monitor diagnostic. IOVDD_UV_EN must be set for the diagnostic to work. The IOVDD_UVn fault flag sets within tp(IOVDD_UV) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
11 | DVDD_OV_DIAG_EN | R/W | 0b | DVDD LDO overvoltage monitor diagnostic enable Enables the DVDD LDO output overvoltage monitor diagnostic. DVDD_OV_EN must be set for the diagnostic to work. The DVDD_OVn fault flag sets within tp(DVDD_OV) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
10 | DVDD_UV_DIAG_EN | R/W | 0b | DVDD LDO undervoltage monitor diagnostic enable Enables the DVDD LDO output undervoltage monitor diagnostic. DVDD_UV_EN must be set for the diagnostic to work. The DVDD_UVn fault flag sets within tp(DVDD_UV) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
9 | AVDD_OSC_DIAG_EN | R/W | 0b | AVDD LDO oscillation monitor diagnostic enable Enables the AVDD LDO output oscillation monitor diagnostic. AVDD_OSC_EN must be set for the diagnostic to work. The AVDD_OSCn fault flag sets within tp(AVDD_OSC) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
8 | IOVDD_OSC_DIAG_EN | R/W | 0b | IOVDD LDO oscillation monitor diagnostic enable Enables the IOVDD LDO output oscillation monitor diagnostic. IOVDD_OSC_EN must be set for the diagnostic to work. The IOVDD_OSCn fault flag sets within tp(IOVDD_OSC) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
7 | DVDD_OSC_DIAG_EN | R/W | 0b | DVDD LDO oscillation monitor diagnostic enable Enables the DVDD LDO output oscillation monitor diagnostic. DVDD_OSC_EN must be set for the diagnostic to work. The DVDD_OSCn fault flag sets within tp(DVDD_OSC) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
6:3 | RESERVED | R | 0000b | Reserved Always reads back 0000b. |
2 | AGNDA_DISC_DIAG_EN | R/W | 0b | AGNDA disconnect monitor diagnostic enable Enables the AGNDA disconnect monitor diagnostic. AGNDA_DISC_EN must be set for the diagnostic to work. The AGNDA_DISCn fault flag sets within tp(AGNDA_OPEN) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
1 | AGNDB_DISC_DIAG_EN | R/W | 0b | AGNDB disconnect monitor diagnostic enable Enables the AGNDB disconnect monitor diagnostic. AGNDB_DISC_EN must be set for the diagnostic to work. The AGNDB_DISCn fault flag sets within tp(AGNDB_OPEN) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
0 | DGND_DISC_DIAG_EN | R/W | 0b | DGND disconnect monitor diagnostic enable Enables the DGND disconnect monitor diagnostic. DGND_DISC_EN must be set for the diagnostic to work. The DGND_DISCn fault flag sets within tp(DGND_OPEN) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[11:0] | |||||||
R/W-000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[11:0] | MCLK_HI_DIAG_EN | MCLK_LO_DIAG_EN | OSCD_WD_DIAG_EN | MCLK_WD_DIAG_EN | |||
R/W-000000000000b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:4 | SPARE[11:0] | R/W | 000000000000b | Spare bits Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings have no effect. |
3 | MCLK_HI_DIAG_EN | R/W | 0b | MCLK frequency too high monitor diagnostic enable Enables the main clock frequency too high monitor diagnostic. MCLK_MON_EN must be set for the diagnostic to work. The MCLK_FAULTn fault flag sets within tp(MCLK_FAULT) when the diagnostic completed successfully. Do not enable the MCLK_LO_DIAG_EN at the same time. Execute the MCLK_HI_DIAG_EN and MCLK_LO_DIAG_EN sequentially. 0b = Disabled 1b = Enabled |
2 | MCLK_LO_DIAG_EN | R/W | 0b | MCLK frequency too low monitor diagnostic enable Enables the main clock frequency too low monitor diagnostic. MCLK_MON_EN must be set for the diagnostic to work. The MCLK_FAULTn fault flag sets within tp(MCLK_FAULT) when the diagnostic completed successfully. Do not enable the MCLK_HI_DIAG_EN at the same time. Execute the MCLK_HI_DIAG_EN and MCLK_LO_DIAG_EN sequentially. 0b = Disabled 1b = Enabled |
1 | OSCD_WD_DIAG_EN | R/W | 0b | Diagnostic oscillator watchdog diagnostic enable Enables the diagnostic oscillator watchdog diagnostic. OSCD_WD_EN must be set for the diagnostic to work. The OSCD_WDn fault flag sets within tp(OSCD_WD) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
0 | MCLK_WD_DIAG_EN | R/W | 0b | Main clock watchdog diagnostic enable Enables the main clock watchdog diagnostic. MCLK_WD_EN must be set for the diagnostic to work. The MCLK_WDn fault flag sets within tp(MCLK_WD) when the diagnostic completed successfully. 0b = Disabled 1b = Enabled |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MEM_MAP_CRC_DIAG[1:0] | ||||||
R-000000b | R/W-00b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIOA_DIAG_EN | GPIOB_DIAG_EN | GPIO_DIAG_EN | ||||
R-00000b | R/W-0b | R/W-0b | R/W-0b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:10 | RESERVED | R | 000000b | Reserved Always reads back 000000b. |
9:8 | MEM_MAP_CRC_DIAG[1:0] | R/W | 00b | Memory map CRC diagnostic bit pattern selection Selects the bit pattern to use for the memory map CRC diagnostic. The MEM_MAP_CRC_FAULTn fault flag sets within tp(MEM_MAP_CRC) when the diagnostic completed successfully. Any of the three available bit patterns can be used for the diagnostic. 00b = Disabled 01b = Pattern 1 10b = Pattern 2 11b = Pattern 3 |
7:3 | RESERVED | R | 00000b | Reserved Always reads back 00000b. |
2 | GPIOA_DIAG_EN | R/W | 0b | GPIOA readback diagnostic enable Inverts the readback value of the GPIxA_DAT[1:0] bits if GPIOxA_DIR is configured as a digital output. 0b = Disabled 1b = Enabled |
1 | GPIOB_DIAG_EN | R/W | 0b | GPIOB readback diagnostic enable Inverts the readback value of the GPIxB_DAT[1:0] bits if GPIOxB_DIR is configured as a digital output. 0b = Disabled 1b = Enabled |
0 | GPIO_DIAG_EN | R/W | 0b | GPIO readback diagnostic enable Inverts the readback value of the GPIx_DAT[1:0] bits if GPIOx_DIR is configured as a digital output. 0b = Disabled 1b = Enabled |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
AVDD_OV_MASK | AVDD_UV_MASK | IOVDD_OV_MASK | IOVDD_UV_MASK | DVDD_OV_MASK | DVDD_UV_MASK | AVDD_OSC_MASK | IOVDD_OSC_MASK |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DVDD_OSC_MASK | AVDD_OTW_MASK | IOVDD_OTW_MASK | AVDD_CL_MASK | IOVDD_CL_MASK | AGNDA_DISC_MASK | AGNDB_DISC_MASK | DGND_DISC_MASK |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | AVDD_OV_MASK | R/W | 0b | AVDD overvoltage fault flag mask Masks the AVDD overvoltage fault flag (AVDD_OVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
14 | AVDD_UV_MASK | R/W | 0b | AVDD undervoltage fault flag mask Masks the AVDD undervoltage fault flag (AVDD_UVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
13 | IOVDD_OV_MASK | R/W | 0b | IOVDD overvoltage fault flag mask Masks the IOVDD overvoltage fault flag (IOVDD_OVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
12 | IOVDD_UV_MASK | R/W | 0b | IOVDD undervoltage fault flag mask Masks the IOVDD undervoltage fault flag (IOVDD_UVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
11 | DVDD_OV_MASK | R/W | 0b | DVDD overvoltage fault flag mask Masks the DVDD overvoltage fault flag (DVDD_OVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
10 | DVDD_UV_MASK | R/W | 0b | DVDD undervoltage fault flag mask Masks the DVDD undervoltage fault flag (DVDD_UVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
9 | AVDD_OSC_MASK | R/W | 0b | AVDD oscillation fault flag mask Masks the AVDD oscillation fault flag (AVDD_OSCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
8 | IOVDD_OSC_MASK | R/W | 0b | IOVDD oscillation fault flag mask Masks the IOVDD oscillation fault flag (IOVDD_OSCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
7 | DVDD_OSC_MASK | R/W | 0b | DVDD oscillation fault flag mask Masks the DVDD oscillation fault flag (DVDD_OSCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
6 | AVDD_OTW_MASK | R/W | 0b | AVDD overtemperature warning flag mask Masks the AVDD LDO overtemperature warning flag (AVDD_OTWn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
5 | IOVDD_OTW_MASK | R/W | 0b | IOVDD overtemperature warning flag mask Masks the IOVDD LDO overtemperature warning flag (IOVDD_OTWn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
4 | AVDD_CL_MASK | R/W | 0b | AVDD current limit flag mask Masks the AVDD LDO current limit flag (AVDD_CLn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
3 | IOVDD_CL_MASK | R/W | 0b | IOVDD current limit flag mask Masks the IOVDD LDO current limit flag (IOVDD_CLn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
2 | AGNDA_DISC_MASK | R/W | 0b | AGNDA pin disconnect detection flag mask Masks the AGNDA pin disconnect detection flag (AGNDA_DISCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
1 | AGNDB_DISC_MASK | R/W | 0b | AGNDB pin disconnect detection flag mask Masks the AGNDB pin disconnect detection flag (AGNDB_DISCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
0 | DGND_DISC_MASK | R/W | 0b | DGND pin disconnect detection flag mask Masks the DGND pin disconnect detection flag (DGND_DISCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | ||||||
R/W-000000b | R-0000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MCLK_FAULT_MASK | OSCD_WD_MASK | MCLK_WD_MASK | ||||
R-0000000b | R/W-0b | R/W-0b | R/W-0b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:10 | RESERVED | R/W | 000000b | Reserved Always write 000000b. |
9:3 | RESERVED | R | 0000000b | Reserved Always reads back 0000000b. |
2 | MCLK_FAULT_MASK | R/W | 0b | MCLK frequency too high or too low fault flag mask Masks the MCLK frequency too high or too low fault flag (MCLK_FAULTn) from triggering the CLOCK_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
1 | OSCD_WD_MASK | R/W | 0b | Diagnostic oscillator watchdog fault flag mask Masks the diagnostic oscillator watchdog fault flag (OSCD_WDn) from triggering the CLOCK_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
0 | MCLK_WD_MASK | R/W | 0b | Main clock watchdog fault flag mask Masks the main clock watchdog fault flag (MCLK_WDn) from triggering the CLOCK_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_MAP1_CRC_FAULT_MASK | REG_MAP2_CRC_FAULT_MASK | REG_MAP3_CRC_FAULT_MASK | RESERVED | MEM_MAP_CRC_FAULT_MASK | RESERVED | ||
R/W-0b | R/W-0b | R/W-0b | R-0b | R/W-0b | R-00000000000b | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | REG_MAP1_CRC_FAULT_MASK | R/W | 0b | Register map section 1 CRC fault flag mask Masks the register map section 1 CRC fault flag (REG_MAP1_CRC_FAULTn) from triggering the DIGITAL_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
14 | REG_MAP2_CRC_FAULT_MASK | R/W | 0b | Register map section 2 CRC fault flag mask Masks the register map section 2 CRC fault flag (REG_MAP2_CRC_FAULTn) from triggering the DIGITAL_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
13 | REG_MAP3_CRC_FAULT_MASK | R/W | 0b | Register map section 3 CRC fault flag mask Masks the register map section 3 CRC fault flag (REG_MAP3_CRC_FAULTn) from triggering the DIGITAL_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
12 | RESERVED | R | 0b | Reserved Always reads back 0b. |
11 | MEM_MAP_CRC_FAULT_MASK | R/W | 0b | Memory map CRC fault flag mask Masks the memory map CRC fault flag (MEM_MAP_CRC_FAULTn) from triggering the DIGITAL_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
10:0 | RESERVED | R | 00000000000b | Reserved Always reads back 00000000000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OCCA_HT_MASK | OCCA_LT_MASK | OCCB_HT_MASK | OCCB_LT_MASK | |||
R-000000000000b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:4 | RESERVED | R | 000000000000b | Reserved Always reads back 000000000000b. |
3 | OCCA_HT_MASK | R/W | 0b | ADC1A overcurrent comparator high threshold fault flag mask Masks the ADC1A overcurrent comparator high threshold fault flag (OCCA_HTn) from triggering the OCC_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
2 | OCCA_LT_MASK | R/W | 0b | ADC1A overcurrent comparator low threshold fault flag mask Masks the ADC1A overcurrent comparator low threshold fault flag (OCCA_LTn) from triggering the OCC_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
1 | OCCB_HT_MASK | R/W | 0b | ADC1B overcurrent comparator high threshold fault flag mask Masks the ADC1B overcurrent comparator high threshold fault flag (OCCB_HTn) from triggering the OCC_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
0 | OCCB_LT_MASK | R/W | 0b | ADC1B overcurrent comparator low threshold fault flag mask Masks the ADC1B overcurrent comparator low threshold fault flag (OCCB_LTn) from triggering the OCC_FAULTn flag in the STATUS_MSB register. 0b = Unmasked 1b = Masked |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SUPPLY_FAULT_MASK | CLOCK_FAULT_MASK | DIGITAL_FAULT_MASK | OCC_FAULT_MASK | SPI_CRC_FAULT_MASK | SPI_TIMEOUT_MASK | SCLK_COUNT_FAULT_MASK |
R-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-1b | R/W-1b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_ACCESS_FAULT_MASK | RESERVED | ||||||
R/W-1b | R-0000000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0b | Reserved Always reads back 0b. |
14 | SUPPLY_FAULT_MASK | R/W | 0b | Supply fault flag mask Masks the supply fault flag (SUPPLY_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output. 0b = Unmasked 1b = Masked |
13 | CLOCK_FAULT_MASK | R/W | 0b | Clock fault flag mask Masks the clock fault flag (CLOCK_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output. 0b = Unmasked 1b = Masked |
12 | DIGITAL_FAULT_MASK | R/W | 0b | Digital fault flag mask Masks the digital fault flag (DIGITAL_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output. 0b = Unmasked 1b = Masked |
11 | OCC_FAULT_MASK | R/W | 0b | Overcurrent comparator fault flag mask Masks the overcurrent comparator fault flag (OCC_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output. 0b = Unmasked 1b = Masked |
10 | SPI_CRC_FAULT_MASK | R/W | 1b | SPI CRC fault flag mask Masks the SPI CRC fault flag (SPI_CRC_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output. 0b = Unmasked 1b = Masked |
9 | SPI_TIMEOUT_MASK | R/W | 1b | SPI timeout fault flag mask Masks the SPI timeout fault flag (SPI_TIMEOUTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output. 0b = Unmasked 1b = Masked |
8 | SCLK_COUNT_FAULT_MASK | R/W | 1b | SCLK counter fault flag mask Masks the SCLK counter fault flag (SCLK_COUNT_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output. 0b = Unmasked 1b = Masked |
7 | REG_ACCESS_FAULT_MASK | R/W | 1b | Register access fault flag mask Masks the register access fault flag (REG_ACCESS_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output. 0b = Unmasked 1b = Masked |
6:0 | RESERVED | R | 0000000b | Reserved Always reads back 00000000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DRDY_CTRL | RESERVED | CLK_SOURCE | WORD_LENGTH | RESERVED | OP_MODE[1:0] | |
R-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0b | R/W-00b | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0b | Reserved Always reads back 0b. |
14 | DRDY_CTRL | R/W | 0b | DRDYn pin control selection Selects which ADC controls the DRDYn pin indication. 0b = ADC1A 1b = ADC1B |
13 | RESERVED | R/W | 0b | Reserved Always write 0b. |
12 | CLK_SOURCE | R/W | 0b | MCLK clock source selection Selects the main clock source of the device. Before changing this bit, all ADCs must be disabled or the device placed in standby or power-down mode. When switching from an external clock to the internal oscillator, the external clock must be provided until after the switch-over is complete. 0b = Internal oscillator 1b = External clock |
11 | WORD_LENGTH | R/W | 0b | Data word length selection Selects the length of every word in the SPI frame. 0b = 24 bits 1b = 32 bits; LSB zero padding |
10 | RESERVED | R | 0b | Reserved Always reads back 0b. |
9:8 | OP_MODE[1:0] | R/W | 00b | Operating mode selection Selects the operating mode for the device. 00b = Active mode 01b = Standby mode (Disables all ADCs) 10b = Power-down mode 11b = Power-down mode |
7:0 | RESERVED | R | 00000000b | Reserved Always reads back 00000000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPIO4_FMT | GPIO3_FMT | GPIO2_FMT | GPIO1_FMT | GPIO0_FMT | GPIO4_DIR | GPIO3_DIR |
R-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO2_DIR | GPIO1_DIR | GPIO0_DIR | GPIO4_SRC | GPIO3_SRC | GPIO2_SRC | RESERVED | GPIO0_SRC |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0b | Reserved Always reads back 0b. |
14 | GPIO4_FMT | R/W | 0b | GPIO4 format Configures GPIO4 for static input and output levels or for PWM input and output levels 0b = When GPIO4 is configured as a digital input: Logic levels are based on static input levels. When GPIO4 is configured as a digital output: Output with static output levels. (GPIO4_LL_PWM_CFG and GPIO4_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case. 1b = When GPIO4 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO4 is configured as a digital output: Output with PWM output defined by the GPIO4_LL_PWM_CFG and GPIO4_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO4_PWM_TB in this case. |
13 | GPIO3_FMT | R/W | 0b | GPIO3 format Configures GPIO3 for static input and output levels or for PWM input and output levels 0b = When GPIO3 is configured as a digital input: Logic levels are based on static input levels. When GPIO3 is configured as a digital output: Output with static output levels. (GPIO3_LL_PWM_CFG and GPIO3_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case. 1b = When GPIO3 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO3 is configured as a digital output: Output with PWM output defined by the GPIO3_LL_PWM_CFG and GPIO3_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO3_PWM_TB in this case. |
12 | GPIO2_FMT | R/W | 0b | GPIO2 format Configures GPIO2 for static input and output levels or for PWM input and output levels 0b = When GPIO2 is configured as a digital input: Logic levels are based on static input levels. When GPIO2 is configured as a digital output: Output with static output levels. (GPIO2_LL_PWM_CFG and GPIO2_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case. 1b = When GPIO2 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO2 is configured as a digital output: Output with PWM output defined by the GPIO2_LL_PWM_CFG and GPIO2_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO2_PWM_TB in this case. |
11 | GPIO1_FMT | R/W | 0b | GPIO1 format Configures GPIO1 for static input and output levels or for PWM input and output levels 0b = When GPIO1 is configured as a digital input: Logic levels are based on static input levels. When GPIO1 is configured as a digital output: Output with static output levels. (GPIO1_LL_PWM_CFG and GPIO1_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case. 1b = When GPIO1 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO1 is configured as a digital output: Output with PWM output defined by the GPIO1_LL_PWM_CFG and GPIO1_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO1_PWM_TB in this case. |
10 | GPIO0_FMT | R/W | 0b | GPIO0 format Configures GPIO0 for static input and output levels or for PWM input and output levels 0b = When GPIO0 is configured as a digital input: Logic levels are based on static input levels. When GPIO0 is configured as a digital output: Output with static output levels. (GPIO0_LL_PWM_CFG and GPIO0_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case. 1b = When GPIO0 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO0 is configured as a digital output: Output with PWM output defined by the GPIO0_LL_PWM_CFG and GPIO0_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO0_PWM_TB in this case. |
9 | GPIO4_DIR | R/W | 0b | GPIO4 direction Configures GPIO4 as a digital input or output. Configure as a digital output when used as OCCB output. 0b = Digital input 1b = Digital output |
8 | GPIO3_DIR | R/W | 0b | GPIO3 direction Configures GPIO3 as a digital input or output. Configure as a digital output when used as OCCA output. 0b = Digital input 1b = Digital output |
7 | GPIO2_DIR | R/W | 0b | GPIO2 direction Configures GPIO2 as a digital input or output. Configure as a digital output when used as FAULT output. 0b = Digital input 1b = Digital output |
6 | GPIO1_DIR | R/W | 0b | GPIO1 direction Configures GPIO1 as a digital input or output. 0b = Digital input 1b = Digital output |
5 | GPIO0_DIR | R/W | 0b | GPIO0 direction Configures GPIO0 as a digital input or output. Configure as a digital output when used as MHD output. 0b = Digital input 1b = Digital output |
4 | GPIO4_SRC | R/W | 0b | GPIO4 data source selection Selects the data source of the GPIO4/OCCB pin when GPIO4 is configured as an output. 0b = OCCB 1b = GPIO |
3 | GPIO3_SRC | R/W | 0b | GPIO3 data source selection Selects the data source of the GPIO3/OCCA pin when GPIO3 is configured as an output. 0b = OCCA 1b = GPIO |
2 | GPIO2_SRC | R/W | 0b | GPIO2 data source selection Selects the data source of the GPIO2/FAULT pin when GPIO2 is configured as an output. 0b = FAULT 1b = GPIO |
1 | RESERVED | R | 0b | Reserved Always reads back 0b. |
0 | GPIO0_SRC | R/W | 0b | GPIO0 data source selection Selects the data source of the GPIO0/MHD pin when GPIO0 is configured as an output. 0b = Missing host detection (MHD) 1b = GPIO |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[10:0] | |||||||
R/W-00000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[10:0] | GPO4_DAT | GPO3_DAT | GPO2_DAT | GPO1_DAT | GPO0_DAT | ||
R/W-00000000000b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:5 | SPARE[10:0] | R/W | 00000000000b | Spare bits Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings have no effect. |
4 | GPO4_DAT | R/W | 0b | GPIO4 output data Output value of GPIO4 when configured as a digital output. Bit setting has not effect when GPIO4 is configured as an input or as OCCB output. 0b = Low 1b = High |
3 | GPO3_DAT | R/W | 0b | GPIO3 output data Output value of GPIO3 when configured as a digital output. Bit setting has not effect when GPIO3 is configured as an input or as OCCA output. 0b = Low 1b = High |
2 | GPO2_DAT | R/W | 0b | GPIO2 output data Output value of GPIO2 when configured as a digital output. Bit setting has not effect when GPIO2 is configured as an input or as FAULT output. 0b = Low 1b = High |
1 | GPO1_DAT | R/W | 0b | GPIO1 output data Output value of GPIO1 when configured as a digital output. Bit setting has not effect when GPIO1 is configured as an input. 0b = Low 1b = High |
0 | GPO0_DAT | R/W | 0b | GPIO0 output data Output value of GPIO0 when configured as a digital output. Bit setting has not effect when GPIO0 is configured as an input or as MHD output. 0b = Low 1b = High |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO0_PWM_TB[1:0] | GPIO0_LL_PWM_HC[6:0] | ||||||
R/W-00b | R/W-0000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO0_LL_PWM_HC[6:0] | GPIO0_LL_PWM_LC[6:0] | ||||||
R/W-0000000b | R/W-1111111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | GPIO0_PWM_TB[1:0] | R/W | 00b | GPIO0/MHD PWM time base selection Selects the time base used for the GPIO0/MHD PWM generation when the GPIO0/MHD pin is configured as an output as well as the time base used for the PWM encoder. 00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz) 01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz) 10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz) 11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz) |
13:7 | GPIO0_LL_PWM_HC[6:0] | R/W | 0000000b | GPIO0/MHD logic low level PWM high counter Sets the high period of the PWM for a logic low level of GPIO0/MHD. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO0/MHD logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO0/MHD logic low level as static low. |
6:0 | GPIO0_LL_PWM_LC[6:0] | R/W | 1111111b | GPIO0/MHD logic low level PWM low counter Sets the low period of the PWM for a logic low level of GPIO0/MHD. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO0/MHD logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO0/MHD logic low level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPIO0_LH_PWM_HC[6:0] | ||||||
R-00b | R/W-1111111b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO0_LH_PWM_HC[6:0] | GPIO0_LH_PWM_LC[6:0] | ||||||
R/W-1111111b | R/W-0000000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R | 00b | Reserved Always reads 00b. |
13:7 | GPIO0_LH_PWM_HC[6:0] | R/W | 1111111b | GPIO0/MHD logic high level PWM high counter Sets the high period of the PWM for a logic high level of GPIO0/MHD. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO0/MHD logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO0/MHD logic high level as static low. |
6:0 | GPIO0_LH_PWM_LC[6:0] | R/W | 0000000b | GPIO0/MHD logic high level PWM low counter Sets the low period of the PWM for a logic high level of GPIO0/MHD. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO0/MHD logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO0/MHD logic high level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO1_PWM_TB[1:0] | GPIO1_LL_PWM_HC[6:0] | ||||||
R/W-00b | R/W-0000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO1_LL_PWM_HC[6:0] | GPIO1_LL_PWM_LC[6:0] | ||||||
R/W-0000000b | R/W-1111111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | GPIO1_PWM_TB[1:0] | R/W | 00b | GPIO1 PWM time base selection Selects the time base used for the GPIO1 PWM generation when the GPIO1 pin is configured as an output as well as the time base used for the PWM encoder. 00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz) 01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz) 10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz) 11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz) |
13:7 | GPIO1_LL_PWM_HC[6:0] | R/W | 0000000b | GPIO1 logic low level PWM high counter Sets the high period of the PWM for a logic low level of GPIO1. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO1 logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO1 logic low level as static low. |
6:0 | GPIO1_LL_PWM_LC[6:0] | R/W | 1111111b | GPIO1 logic low level PWM low counter Sets the low period of the PWM for a logic low level of GPIO1. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO1 logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO1 logic low level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPIO1_LH_PWM_HC[6:0] | ||||||
R-00b | R/W-1111111b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO1_LH_PWM_HC[6:0] | GPIO1_LH_PWM_LC[6:0] | ||||||
R/W-1111111b | R/W-0000000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R | 00b | Reserved Always reads 00b. |
13:7 | GPIO1_LH_PWM_HC[6:0] | R/W | 1111111b | GPIO1 logic high level PWM high counter Sets the high period of the PWM for a logic high level of GPIO1. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO1 logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO1 logic high level as static low. |
6:0 | GPIO1_LH_PWM_LC[6:0] | R/W | 0000000b | GPIO1 logic high level PWM low counter Sets the low period of the PWM for a logic high level of GPIO1. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO1 logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO1 logic high level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO2_PWM_TB[1:0] | GPIO2_LL_PWM_HC[6:0] | ||||||
R/W-00b | R/W-0000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO2_LL_PWM_HC[6:0] | GPIO2_LL_PWM_LC[6:0] | ||||||
R/W-0000000b | R/W-1111111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | GPIO2_PWM_TB[1:0] | R/W | 00b | GPIO2/FAULT PWM time base selection Selects the time base used for the GPIO2/FAULT PWM generation when the GPIO2/FAULT pin is configured as an output as well as the time base used for the PWM encoder. 00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz) 01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz) 10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz) 11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz) |
13:7 | GPIO2_LL_PWM_HC[6:0] | R/W | 0000000b | GPIO2/FAULT logic low level PWM high counter Sets the high period of the PWM for a logic low level of GPIO2/FAULT. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO2/FAULT logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/FAULT logic low level as static low. |
6:0 | GPIO2_LL_PWM_LC[6:0] | R/W | 1111111b | GPIO2/FAULT logic low level PWM low counter Sets the low period of the PWM for a logic low level of GPIO2/FAULT. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO2/FAULT logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/FAULT logic low level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPIO2_LH_PWM_HC[6:0] | ||||||
R-00b | R/W-1111111b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO2_LH_PWM_HC[6:0] | GPIO2_LH_PWM_LC[6:0] | ||||||
R/W-1111111b | R/W-0000000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R | 00b | Reserved Always reads 00b. |
13:7 | GPIO2_LH_PWM_HC[6:0] | R/W | 1111111b | GPIO2/FAULT logic high level PWM high counter Sets the high period of the PWM for a logic high level of GPIO2/FAULT. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO2/FAULT logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/FAULT logic high level as static low. |
6:0 | GPIO2_LH_PWM_LC[6:0] | R/W | 0000000b | GPIO2/FAULT logic high level PWM low counter Sets the low period of the PWM for a logic high level of GPIO2/FAULT. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO2/FAULT logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/FAULT logic high level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO3_PWM_TB[1:0] | GPIO3_LL_PWM_HC[6:0] | ||||||
R/W-00b | R/W-0000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO3_LL_PWM_HC[6:0] | GPIO3_LL_PWM_LC[6:0] | ||||||
R/W-0000000b | R/W-1111111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | GPIO3_PWM_TB[1:0] | R/W | 00b | GPIO3/OCCA PWM time base selection Selects the time base used for the GPIO3/OCCA PWM generation when the GPIO3/OCCA pin is configured as an output as well as the time base used for the PWM encoder. 00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz) 01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz) 10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz) 11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz) |
13:7 | GPIO3_LL_PWM_HC[6:0] | R/W | 0000000b | GPIO3/OCCA logic low level PWM high counter Sets the high period of the PWM for a logic low level of GPIO3/OCCA. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO3/OCCA logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO3/OCCA logic low level as static low. |
6:0 | GPIO3_LL_PWM_LC[6:0] | R/W | 1111111b | GPIO3/OCCA logic low level PWM low counter Sets the low period of the PWM for a logic low level of GPIO3/OCCA. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO3/OCCA logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO3/OCCA logic low level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPIO3_LH_PWM_HC[6:0] | ||||||
R-00b | R/W-1111111b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO3_LH_PWM_HC[6:0] | GPIO3_LH_PWM_LC[6:0] | ||||||
R/W-1111111b | R/W-0000000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R | 00b | Reserved Always reads 00b. |
13:7 | GPIO3_LH_PWM_HC[6:0] | R/W | 1111111b | GPIO3/OCCA logic high level PWM high counter Sets the high period of the PWM for a logic high level of GPIO3/OCCA. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO3/OCCA logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/OCCA logic high level as static low. |
6:0 | GPIO3_LH_PWM_LC[6:0] | R/W | 0000000b | GPIO3/OCCA logic high level PWM low counter Sets the low period of the PWM for a logic high level of GPIO3/OCCA. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO3/OCCA logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/OCCA logic high level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO4_PWM_TB[1:0] | GPIO4_LL_PWM_HC[6:0] | ||||||
R/W-00b | R/W-0000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO4_LL_PWM_HC[6:0] | GPIO4_LL_PWM_LC[6:0] | ||||||
R/W-0000000b | R/W-1111111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | GPIO4_PWM_TB[1:0] | R/W | 00b | GPIO4/OCCB PWM time base selection Selects the time base used for the GPIO4/OCCB PWM generation when the GPIO4/OCCB pin is configured as an output as well as the time base used for the PWM encoder 00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz) 01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz) 10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz) 11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz) |
13:7 | GPIO4_LL_PWM_HC[6:0] | R/W | 0000000b | GPIO4/OCCB logic low level PWM high counter Sets the high period of the PWM for a logic low level of GPIO4/OOCB. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO4/OCCB logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO4/OCCB logic low level as static low. |
6:0 | GPIO4_LL_PWM_LC[6:0] | R/W | 1111111b | GPIO4/OCCB logic low level PWM low counter Sets the low period of the PWM for a logic low level of GPIO4/OCCB. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO4/OCCB logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO4/OCCB logic low level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPIO4_LH_PWM_HC[6:0] | ||||||
R-00b | R/W-1111111b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO4_LH_PWM_HC[6:0] | GPIO4_LH_PWM_LC[6:0] | ||||||
R/W-1111111b | R/W-0000000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R | 00b | Reserved Always reads 00b. |
13:7 | GPIO4_LH_PWM_HC[6:0] | R/W | 1111111b | GPIO4BOCCB logic high level PWM high counter Sets the high period of the PWM for a logic high level of GPIO4. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM high time = (PWM high counter value x PWM time base) Setting the PWM high counter value to 0000000b configures the GPIO4 logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO4/OCCB logic high level as static low. |
6:0 | GPIO4_LH_PWM_LC[6:0] | R/W | 0000000b | GPIO4/OCCB logic high level PWM low counter Sets the low period of the PWM for a logic high level of GPIO4/OCCB. PWM period = (PWM high counter value + PWM low counter value) x PWM time base PWM low time = (PWM low counter value x PWM time base) Setting the PWM low counter value to 0000000b configures the GPIO4/OCCB logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO4/OCCB logic high level as static low. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[15:0] | |||||||
R/W-0101010101010101b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[15:0] | |||||||
R/W-0101010101010101b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SPARE[15:0] | R/W | 0101010101010101b | Spare bits Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_MAP1_CRC_VALUE[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_MAP1_CRC_VALUE[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | REG_MAP1_CRC_VALUE[15:0] | R/W | 0000000000000000b | Register map CRC value for section 1 Register map CRC value for section 1. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_MAP2_CRC_EN | RESERVED | ||||||
R/W-0b | R-000000000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TDACA_VALUE[2:0] | ||||||
R-000000000000b | R/W-000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | REG_MAP2_CRC_EN | R/W | 0b | Register map section 2 CRC enable Enables the register map CRC for section 2 (register address space from 80h to A3h). 0b = Disabled 1b = Enabled |
14:3 | RESERVED | R | 000000000000b | Reserved Always reads 000000000000b. |
2:0 | TDACA_VALUE[2:0] | R/W | 000b | Test DAC A output value Selects the output value of Test DAC A. 000b = 1 x VREFA/40 001b = 2 x VREFA/40 010b = 4 x VREFA/40 011b = 9 x VREFA/40 100b = 18 x VREFA/40 101b = 36 x VREFA/40 110b = –4 x VREFA/40 111b = –9 x VREFA/40 |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SPARE[2:0] | GPIO1A_FMT | GPIO0A_FMT | GPIO1A_DIR | GPIO0A_DIR | ||
R-1b | R/W-000b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO1A_PWM_TB[1:0] | GPIO0A_PWM_TB[1:0] | SPARE[1:0] | GPO1A_DAT | GPO0A_DAT | |||
R/W-00b | R/W-00b | R/W-00b | R/W-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 1b | Reserved Always reads 1b. |
14:12 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
11 | GPIO1A_FMT | R/W | 0b | GPIO1A format Configures GPIO1A for static input and output levels or for PWM input levels. 0b = When GPIO1A is configured as a digital input: Logic levels are based on static input levels. When GPIO1A is configured as a digital output: Output with static output levels. 1b = When GPIO1A is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO1A is configured as a digital output: Output with static output levels. GPIO1A does not have PWM output capability. |
10 | GPIO0A_FMT | R/W | 0b | GPIO0A format Configures GPIO0A for static input and output levels or for PWM input levels. 0b = When GPIO0A is configured as a digital input: Logic levels are based on static input levels. When GPIO0A is configured as a digital output: Output with static output levels. 1b = When GPIO0A is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO0A is configured as a digital output: Output with static output levels. GPIO0A does not have PWM output capability. |
9 | GPIO1A_DIR | R/W | 0b | GPIO1A direction Configures GPIO1A as a digital input or digital output. 0b = Digital input 1b = Digital output |
8 | GPIO0A_DIR | R/W | 0b | GPIO0A direction Configures GPIO0A as a digital input or digital output. 0b = Digital input 1b = Digital output |
7:6 | GPIO1A_PWM_TB[1:0] | R/W | 00b | GPIO1A PWM time base selection Selects the time base used for the PWM encoder when GPIO1A is configured as a digital input. 00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz) 01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz) 10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz) 11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz) |
5:4 | GPIO0A_PWM_TB[1:0] | R/W | 00b | GPIO0A PWM time base selection Selects the time base used for the PWM encoder when GPIO0A is configured as a digital input. 00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz) 01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz) 10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz) 11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz) |
3:2 | SPARE[1:0] | R/W | 00b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
1 | GPO1A_DAT | R/W | 0b | GPIO1A output data Output value of GPIO1A when configured as a digital output. Bit setting has not effect when GPIO1A is configured as a digital input. 0b = Low 1b = High |
0 | GPO0A_DAT | R/W | 0b | GPIO0A output data Output value of GPIO0A when configured as a digital output. Bit setting has not effect when GPIO0A is configured as a digital input. 0b = Low 1b = High |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CONV_MODE1A | OSR1A[2:0] | |||||
R-0000b | R/W-0b | R/W-100b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GC1A_EN | GC1A_DELAY[2:0] | |||||
R-0000b | R/W-0b | R/W-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
11 | CONV_MODE1A | R/W | 0b | Conversion mode selection Selects the conversion mode for ADC1A. 0b = Continuous-conversion mode 1b = Single-shot conversion mode |
10:8 | OSR1A[2:0] | R/W | 100b | Oversampling ratio selection Selects the oversampling ratio for ADC1A. The data rate calculates to fMOD / OSR. 000b = 64 001b = 128 010b = 256 011b = 512 100b = 1024 101b = 2048 110b = 4096 111b = 8192 |
7:4 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
3 | GC1A_EN | R/W | 0b | Global-chop mode enable Enables the global-chop mode for ADC1A. 0b = Disabled 1b = Enabled |
2:0 | GC1A_DELAY[2:0] | R/W | 000b | Global-chop mode delay time selection Selects the delay time in global-chop mode for ADC1A. 000b = 2 x tMOD 001b = 4 x tMOD 010b = 8 x tMOD 011b = 16 x tMOD 100b = 32 x tMOD 101b = 64 x tMOD 110b = 128 x tMOD 111b = 256 x tMOD |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ADC1A_EN | RESERVED | GAIN1A[1:0] | MUX1A[1:0] | ||||
R/W-1b | R-000b | R/W-00b | R/W-00b | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OWD1A_SOURCE_MUX | OWD1A_SINK_MUX | OWD1A_SOURCE_VALUE[1:0] | OWD1A_SINK_VALUE[1:0] | |||
R-00b | R/W-0b | R/W-1b | R/W-00b | R/W-00b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | ADC1A_EN | R/W | 1b | ADC1A enable Enables ADC1A. The conversion data of ADC1A reset to 000000h and the conversion counter CONV1A_COUNT[1:0] resets to 00b when ADC1A is disabled or when the device is put in standby or power-down mode. 0b = Disabled 1b = Enabled |
14:12 | RESERVED | R | 000b | Reserved Always reads 000b. |
11:10 | GAIN1A[1:0] | R/W | 00b | ADC1A gain selection Selects the gain (FSR = full scale range) of ADC1A. Gains 16 and 32 are digital gains using analog gain = 8. 00b = 4 01b = 8 10b = 16 11b = 32 |
9:8 | MUX1A[1:0] | R/W | 00b | ADC1A multiplexer channel selection Selects the multiplexer channel for ADC1A. 00b = AINp = CPA, AINn = CNA 01b = AINp = CNA, AINn = CPA 10b = Internal short to AGNDA. Analog inputs CPA, CNA disconnected from ADC1A. 11b = Test DAC B output |
7:6 | RESERVED | R | 00b | Reserved Always reads 00b. |
5 | OWD1A_SOURCE_MUX | R/W | 0b | ADC1A current source multiplexer selection Selects the multiplexer channel for the ADC1A current source. 0b = CPA 1b = CNA |
4 | OWD1A_SINK_MUX | R/W | 1b | ADC1A current sink multiplexer selection Selects the multiplexer channel for the ADC1A current sink. 0b = CPA 1b = CNA |
3:2 | OWD1A_SOURCE_VALUE[1:0] | R/W | 00b | ADC1A current source value selection Selects the current value for the ADC1A current source. 00b = Off 01b = 4 µA 10b = 40 µA 11b = 240 µA |
1:0 | OWD1A_SINK_VALUE[1:0] | R/W | 00b | ADC1A current sink value selection Selects the current value for the ADC1A current sink. 00b = Off 01b = 4 µA 10b = 40 µA 11b = 240 µA |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL1A[23:8] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL1A[23:8] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL1A[23:8] | R/W | 0000000000000000b | ADC1A offset calibration bits [23:8] Value provided in two's complement format. LSB size = (2 x VREFA) / (GAIN1A x 224) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL1A[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL1A[7:0] | R/W | 00000000b | ADC1A offset calibration bits [7:0] Value provided in two's complement format. LSB size = (2 x VREFA) / (GAIN1A x 224) |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL1A[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL1A[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL1A[15:0] | R/W | 0000000000000000b | ADC1A gain calibration bits [15:0] Value provided in two's complement format. LSB size = 1/216 = 0.000015 Mapping: 0111111111111111b = 1.499985 0000000000000001b = 1.000015 0000000000000000b = 1 1111111111111111b = 0.999985 1000000000000000b = 0.5 |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCCA_EN | OCCA_POL | RESERVED | OCCA_NUM[4:0] | ||||
R/W-0b | R/W-0b | R/W-0b | R/W-00000b | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | OCCA_EN | R/W | 0b | ADC1A overcurrent comparator enable Enables the digital fast filter and digital comparator on ADC1A. ADC1A must be enabled to use the overcurrent comparator. The fast filter is not affected by the STARTA and STOPA bits. 0b = Disabled 1b = Enabled |
14 | OCCA_POL | R/W | 0b | OCCA pin polarity selection Selects the polarity of the OCCA pin. The actual output behavior of the GPIO3/OCCA pin, when configured as OCCA output in the GPIO3_SRC bit, depends on the GPIO3_FMT setting. An OCCA fault is active when any of the OCCA_HTn or OCCA_LTn bits are active. 0b = Active low. In case of a fault a logic low level is driven. 1b = Active high. In case of a fault a logic high level is driven. |
13 | RESERVED | R/W | 0b | Reserved Always write 0b. |
12:8 | OCCA_NUM[4:0] | R/W | 00000b | ADC1A overcurrent comparator deglitch filter selection Selects the number of conversions the output of the ADC1A digital fast filter must exceed the set high or low thresholds to trip the OCCA_HTn or OCCA_LTn comparator output. The fast filter path uses a SINC3 filter with a fixed OSR = 64. The counter starts again whenever the digital fast filter output falls below the threshold, means there is no hysteresis. 00000b = 1 00001b = 2 00010b = 3 00011b = 4 00100b = 5 00101b = 6 00110b = 7 00111b = 8 01000b = 9 01001b = 10 01010b = 12 01011b = 14 01100b = 16 01101b = 18 01110b = 20 01111b = 22 10000b = 24 10001b = 26 10010b = 28 10011b = 32 10100b = 40 10101b = 48 10110b = 56 10111b = 64 11000b = 72 11001b = 80 11010b = 88 11011b = 96 11100b = 104 11101b = 112 11110b = 120 11111b = 128 |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 00000000b |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCCA_HIGH_TH[15:0] | |||||||
R/W-0111111111111111b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCCA_HIGH_TH[15:0] | |||||||
R/W-0111111111111111b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCCA_HIGH_TH[15:0] | R/W | 0111111111111111b | ADC1A overcurrent comparator high threshold bits [15:0] Value provided in two's complement format. LSB size = (2 x VREFA) / (GAIN1A x 216) Values larger than the high threshold trigger an OCCA_HTn event. Setting the value to +FS (= 7FFFh) disables the high threshold detection. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCCA_LOW_TH[15:0] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCCA_LOW_TH[15:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCCA_LOW_TH[15:0] | R/W | 1000000000000000b | ADC1A overcurrent comparator low threshold bits [15:0] Value provided in two's complement format. LSB size = (2 x VREFA) / (GAIN1A x 216) Values smaller than the low threshold trigger an OCCA_LTn event. Setting the value to –FS (= 8000h) disables the low threshold detection. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[15:0] | |||||||
R/W-0101010101010101b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[15:0] | |||||||
R/W-0101010101010101b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SPARE[15:0] | R/W | 0101010101010101b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ADC2A_EN | RESERVED | VCMA_EN | OWD2A_SOURCE_MUX[2:0] | ||||
R/W-1b | R-0000b | R/W-0b | R/W-000b | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OWD2A_SOURCE_MUX[2:0] | OWD2A_SINK_MUX[2:0] | OWD2A_SOURCE_VALUE[1:0] | OWD2A_SINK_VALUE[1:0] | ||||
R/W-000b | R/W-001b | R/W-00b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | ADC2A_EN | R/W | 1b | ADC2A enable Enables ADC2A. Only change settings of registers from address 8Ch to 9Fh of ADC2A when ADC2A is disabled. The conversion data of ADC2A reset to 0000h and the sequence counter SEQ2A_COUNT[1:0] resets to 00b when ADC2A is disabled or when the device is put in standby or power-down mode. 0b = Disabled 1b = Enabled |
14:11 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
10 | VCMA_EN | R/W | 0b | Common-mode output buffer VCMA enable Enables the common-mode output buffer VCMA on analog input V7A. 0b = Disabled 1b = Enabled |
9:7 | OWD2A_SOURCE_MUX[2:0] | R/W | 000b | ADC2A current source multiplexer selection Selects the multiplexer channel for the ADC2A current source. 000b = V0A 001b = V1A 010b = V2A 011b = V3A 100b = V4A 101b = V5A 110b = V6A 111b = V7A |
6:4 | OWD2A_SINK_MUX[2:0] | R/W | 001b | ADC2A current sink multiplexer selection Selects the multiplexer channel for the ADC2A current sink. 000b = V0A 001b = V1A 010b = V2A 011b = V3A 100b = V4A 101b = V5A 110b = V6A 111b = V7A |
3:2 | OWD2A_SOURCE_VALUE[1:0] | R/W | 00b | ADC2A current source value selection Selects the current value for the ADC2A current source. 00b = Off 01b = 4 µA 10b = 40 µA 11b = 240 µA |
1:0 | OWD2A_SINK_VALUE[1:0] | R/W | 00b | ADC2A current sink value selection Selects the current value for the ADC2A current sink. 00b = Off 01b = 4 µA 10b = 40 µA 11b = 240 µA |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_MODE[1:0] | RESERVED | MUX2A_DELAY[2:0] | |||||
R/W-00b | R-000b | R/W-000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OSR2A[1:0] | ||||||
R-000000b | R/W-00b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | SEQ2A_MODE[1:0] | R/W | 00b | ADC2A sequencer mode selection Selects the way the ADC2A sequencer starts a new sequence. Setting the SEQ2A_START bit always aborts and restarts an ongoing sequence in all modes. 00b = Single-shot sequence mode based on SEQ2A_START bit (ADC2A runs one time through the sequence after the SEQ2A_START bit is set) 01b = Single-shot sequence mode based on ADC1A conversion starts or SEQ2A_START bit. This setting is only useful when ADC1A is configured for continuous-conversion mode. Sequences are started at the falling edge of DRDYAn or when the SEQ2A_START bit is set. Conversion starts triggered by the DRDYAn signal are ignored, that is do not abort and restart a sequence, while a sequence is ongoing. 10b = Continuous sequence mode based on SEQ2A_START bit 11b = Continuous sequence mode based on SEQ2A_START bit |
13:11 | RESERVED | R | 000b | Reserved Always reads 00b. |
10:8 | MUX2A_DELAY[2:0] | R/W | 000b | ADC2A multiplexer delay time selection Selects the delay time before starting conversion on the next sequence step. 000b = 16 x tMCLK (= 2 µs for fMCLK = 8.192 MHz) 001b = 64 x tMCLK (= 7.8 µs for fMCLK = 8.192 MHz) 010b = 128 x tMCLK (= 15.6 µs for fMCLK = 8.192 MHz) 011b = 256 x tMCLK (= 31.2 µs for fMCLK = 8.192 MHz) 100b = 512 x tMCLK (= 62.5 µs for fMCLK = 8.192 MHz) 101b = 1024 x tMCLK (= 124.9 µs for fMCLK = 8.192 MHz) 110b = 2048 x tMCLK (= 249.9 µs for fMCLK = 8.192 MHz) 111b = 4096 x tMCLK (= 499.7 µs for fMCLK = 8.192 MHz) |
7:2 | RESERVED | R | 000000b | Reserved Always reads 000000b. |
1:0 | OSR2A[1:0] | R/W | 00b | ADC2A oversampling ratio selection Selects the oversampling ratio for ADC2A. 00b = 64 (SINC3 OSR = 64, conversion time = 384 x tMCLK) 01b = 128 (SINC3 OSR = 64, SINC1 OSR = 2, conversion time = 512 x tMCLK) 10b = 256 (SINC3 OSR = 64, SINC1 OSR = 4, conversion time = 768 x tMCLK) 11b = 512 (SINC3 OSR = 64, SINC1 OSR = 8, conversion time = 1280 x tMCLK) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
7:0 | SPARE[7:0] | R/W | 00000000b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL2A[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL2A[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL2A[15:0] | R/W | 0000000000000000b | ADC2A offset calibration bits [15:0] Value provided in two's complement format. GAIN2A = 1: LSB size = (2 x VREFA) / 216 GAIN2A = 2, 4: LSB size = (2 x VREFA) / (2 x 216) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL2A[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL2A[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL2A[15:0] | R/W | 0000000000000000b | ADC2A gain calibration bits [15:0] Value provided in two's complement format. LSB size = 1/216 = 0.000015 Mapping: 0111111111111111b = 1.499985 0000000000000001b = 1.000015 0000000000000000b = 1 1111111111111111b = 0.999985 1000000000000000b = 0.5 |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP0_EN | SEQ2A_STEP0_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP0_CH_N | SEQ2A_STEP0_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-0000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP0_EN | R/W | 0b | ADC2A sequence step 0 enable Enables sequence step 0 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP0_GAIN[1:0] | R/W | 00b | ADC2A sequence step 0 gain selection Selects the gain of ADC2A for sequence step 0. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP0_CH_N | R/W | 0b | ADC2A sequence step 0 negative input channel selection Selects the negative ADC2A analog input for sequence step 0. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP0_CH_P[3:0] | R/W | 0000b | ADC2A sequence step 0 positive input channel selection Selects the positive ADC2A analog input for sequence step 0. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP0_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP1_EN | SEQ2A_STEP1_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP1_CH_N | SEQ2A_STEP1_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-0001b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP1_EN | R/W | 0b | ADC2A sequence step 1 enable Enables sequence step 1 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP1_GAIN[1:0] | R/W | 00b | ADC2A sequence step 1 gain selection Selects the gain of ADC2A for sequence step 1. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP1_CH_N | R/W | 0b | ADC2A sequence step 1 negative input channel selection Selects the negative ADC2A analog input for sequence step 1. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP1_CH_P[3:0] | R/W | 0001b | ADC2A sequence step 1 positive input channel selection Selects the positive ADC2A analog input for sequence step 1. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP1_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP2_EN | SEQ2A_STEP2_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP2_CH_N | SEQ2A_STEP2_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-0010b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP2_EN | R/W | 0b | ADC2A sequence step 2 enable Enables sequence step 2 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP2_GAIN[1:0] | R/W | 00b | ADC2A sequence step 2 gain selection Selects the gain of ADC2A for sequence step 2. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP2_CH_N | R/W | 0b | ADC2A sequence step 2 negative input channel selection Selects the negative ADC2A analog input for sequence step 2. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP2_CH_P[3:0] | R/W | 0010b | ADC2A sequence step 2 positive input channel selection Selects the positive ADC2A analog input for sequence step 2. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP2_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP3_EN | SEQ2A_STEP3_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP3_CH_N | SEQ2A_STEP3_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-0011b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP3_EN | R/W | 0b | ADC2A sequence step 3 enable Enables sequence step 3 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP3_GAIN[1:0] | R/W | 00b | ADC2A sequence step 3 gain selection Selects the gain of ADC2A for sequence step 3. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP3_CH_N | R/W | 0b | ADC2A sequence step 3 negative input channel selection Selects the negative ADC2A analog input for sequence step 3. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP3_CH_P[3:0] | R/W | 0011b | ADC2A sequence step 3 positive input channel selection Selects the positive ADC2A analog input for sequence step 3. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP3_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP4_EN | SEQ2A_STEP4_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP4_CH_N | SEQ2A_STEP4_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-0100b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP4_EN | R/W | 0b | ADC2A sequence step 4 enable Enables sequence step 4 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP4_GAIN[1:0] | R/W | 00b | ADC2A sequence step 4 gain selection Selects the gain of ADC2A for sequence step 4. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP4_CH_N | R/W | 0b | ADC2A sequence step 4 negative input channel selection Selects the negative ADC2A analog input for sequence step 4. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP4_CH_P[3:0] | R/W | 0100b | ADC2A sequence step 4 positive input channel selection Selects the positive ADC2A analog input for sequence step 4. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP4_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP5_EN | SEQ2A_STEP5_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP5_CH_N | SEQ2A_STEP5_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-0101b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP5_EN | R/W | 0b | ADC2A sequence step 5 enable Enables sequence step 5 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP5_GAIN[1:0] | R/W | 00b | ADC2A sequence step 5 gain selection Selects the gain of ADC2A for sequence step 5. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP5_CH_N | R/W | 0b | ADC2A sequence step 5 negative input channel selection Selects the negative ADC2A analog input for sequence step 5. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP5_CH_P[3:0] | R/W | 0101b | ADC2A sequence step 5 positive input channel selection Selects the positive ADC2A analog input for sequence step 5. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP5_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP6_EN | SEQ2A_STEP6_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP6_CH_N | SEQ2A_STEP6_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-0110b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP6_EN | R/W | 0b | ADC2A sequence step 6 enable Enables sequence step 6 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP6_GAIN[1:0] | R/W | 00b | ADC2A sequence step 6 gain selection Selects the gain of ADC2A for sequence step 6. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP6_CH_N | R/W | 0b | ADC2A sequence step 6 negative input channel selection Selects the negative ADC2A analog input for sequence step 6. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP6_CH_P[3:0] | R/W | 0110b | ADC2A sequence step 6 positive input channel selection Selects the positive ADC2A analog input for sequence step 6. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP6_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP7_EN | SEQ2A_STEP7_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP7_CH_N | SEQ2A_STEP7_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-0111b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP7_EN | R/W | 0b | ADC2A sequence step 7 enable Enables sequence step 7 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP7_GAIN[1:0] | R/W | 00b | ADC2A sequence step 7 gain selection Selects the gain of ADC2A for sequence step 7. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP7_CH_N | R/W | 0b | ADC2A sequence step 7 negative input channel selection Selects the negative ADC2A analog input for sequence step 7. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP7_CH_P[3:0] | R/W | 0111b | ADC2A sequence step 7 positive input channel selection Selects the positive ADC2A analog input for sequence step 7. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP7_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP8_EN | SEQ2A_STEP8_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP8_CH_N | SEQ2A_STEP8_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-1000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP8_EN | R/W | 0b | ADC2A sequence step 8 enable Enables sequence step 8 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP8_GAIN[1:0] | R/W | 00b | ADC2A sequence step 8 gain selection Selects the gain of ADC2A for sequence step 8. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP8_CH_N | R/W | 0b | ADC2A sequence step 8 negative input channel selection Selects the negative ADC2A analog input for sequence step 8. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP8_CH_P[3:0] | R/W | 1000b | ADC2A sequence step 8 positive input channel selection Selects the positive ADC2A analog input for sequence step 8. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP8_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP9_EN | SEQ2A_STEP9_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP9_CH_N | SEQ2A_STEP9_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-1001b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP9_EN | R/W | 0b | ADC2A sequence step 9 enable Enables sequence step 9 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP9_GAIN[1:0] | R/W | 00b | ADC2A sequence step 9 gain selection Selects the gain of ADC2A for sequence step 9. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP9_CH_N | R/W | 0b | ADC2A sequence step 9 negative input channel selection Selects the negative ADC2A analog input for sequence step 9. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP9_CH_P[3:0] | R/W | 1001b | ADC2A sequence step 9 positive input channel selection Selects the positive ADC2A analog input for sequence step 9. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP9_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP10_EN | SEQ2A_STEP10_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP10_CH_N | SEQ2A_STEP10_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-1010b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP10_EN | R/W | 0b | ADC2A sequence step 10 enable Enables sequence step 10 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP10_GAIN[1:0] | R/W | 00b | ADC2A sequence step 10 gain selection Selects the gain of ADC2A for sequence step 10. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP10_CH_N | R/W | 0b | ADC2A sequence step 10 negative input channel selection Selects the negative ADC2A analog input for sequence step 10. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP10_CH_P[3:0] | R/W | 1010b | ADC2A sequence step 10 positive input channel selection Selects the positive ADC2A analog input for sequence step 10. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP10_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP11_EN | SEQ2A_STEP11_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP11_CH_N | SEQ2A_STEP11_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-1011b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP11_EN | R/W | 0b | ADC2A sequence step 11 enable Enables sequence step 11 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP11_GAIN[1:0] | R/W | 00b | ADC2A sequence step 11 gain selection Selects the gain of ADC2A for sequence step 11. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP11_CH_N | R/W | 0b | ADC2A sequence step 11 negative input channel selection Selects the negative ADC2A analog input for sequence step 11. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP11_CH_P[3:0] | R/W | 1011b | ADC2A sequence step 11 positive input channel selection Selects the positive ADC2A analog input for sequence step 11. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP11_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP12_EN | SEQ2A_STEP12_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP12_CH_N | SEQ2A_STEP12_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-1100b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP12_EN | R/W | 0b | ADC2A sequence step 12 enable Enables sequence step 12 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP12_GAIN[1:0] | R/W | 00b | ADC2A sequence step 12 gain selection Selects the gain of ADC2A for sequence step 12. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP12_CH_N | R/W | 0b | ADC2A sequence step 12 negative input channel selection Selects the negative ADC2A analog input for sequence step 12. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP12_CH_P[3:0] | R/W | 1100b | ADC2A sequence step 12 positive input channel selection Selects the positive ADC2A analog input for sequence step 12. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP12_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP13_EN | SEQ2A_STEP13_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP13_CH_N | SEQ2A_STEP13_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-1101b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP13_EN | R/W | 0b | ADC2A sequence step 13 enable Enables sequence step 13 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP13_GAIN[1:0] | R/W | 00b | ADC2A sequence step 13 gain selection Selects the gain of ADC2A for sequence step 13. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP13_CH_N | R/W | 0b | ADC2A sequence step 13 negative input channel selection Selects the negative ADC2A analog input for sequence step 13. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP13_CH_P[3:0] | R/W | 1101b | ADC2A sequence step 13 positive input channel selection Selects the positive ADC2A analog input for sequence step 13. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP13_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP14_EN | SEQ2A_STEP14_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP14_CH_N | SEQ2A_STEP14_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-1110b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP14_EN | R/W | 0b | ADC2A sequence step 14 enable Enables sequence step 14 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP14_GAIN[1:0] | R/W | 00b | ADC2A sequence step 14 gain selection Selects the gain of ADC2A for sequence step 14. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP14_CH_N | R/W | 0b | ADC2A sequence step 14 negative input channel selection Selects the negative ADC2A analog input for sequence step 14. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP14_CH_P[3:0] | R/W | 1110b | ADC2A sequence step 14 positive input channel selection Selects the positive ADC2A analog input for sequence step 14. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP14_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQ2A_STEP15_EN | SEQ2A_STEP15_GAIN[1:0] | RESERVED | |||||
R/W-0b | R/W-00b | R-00000000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEQ2A_STEP15_CH_N | SEQ2A_STEP15_CH_P[3:0] | |||||
R-00000000b | R/W-0b | R/W-1111b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SEQ2A_STEP15_EN | R/W | 0b | ADC2A sequence step 15 enable Enables sequence step 15 of the ADC2A sequencer. 0b = Disabled 1b = Enabled |
14:13 | SEQ2A_STEP15_GAIN[1:0] | R/W | 00b | ADC2A sequence step 15 gain selection Selects the gain of ADC2A for sequence step 15. 00b = 1 01b = 2 10b = 4 11b = 4 |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4 | SEQ2A_STEP15_CH_N | R/W | 0b | ADC2A sequence step 15 negative input channel selection Selects the negative ADC2A analog input for sequence step 15. 0b = AGNDA 1b = V7A |
3:0 | SEQ2A_STEP15_CH_P[3:0] | R/W | 1111b | ADC2A sequence step 15 positive input channel selection Selects the positive ADC2A analog input for sequence step 15. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP15_CH_N bit has no effect. 0000b = V0A 0001b = V1A 0010b = V2A 0011b = V3A 0100b = V4A 0101b = V5A 0110b = V6A 0111b = V7A 1000b = Temperature sensor A (negative ADC input is automatically selected) 1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected) 1010b = Test DAC B (negative ADC input is automatically selected) 1011b = AVDD/4 (negative ADC input is automatically selected) 1100b = IOVDD/4 (negative ADC input is automatically selected) 1101b = DVDD/2 (negative ADC input is automatically selected) 1110b = APWR/103 (negative ADC input is automatically selected) 1111b = DPWR/103 (negative ADC input is automatically selected) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SPARE[1:0] | RESERVED | |||||
R-0000b | R/W-00b | R-1000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[1:0] | RESERVED | |||||
R-1000b | R/W-01b | R-0000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
11:10 | SPARE[1:0] | R/W | 00b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
9:6 | RESERVED | R | 1000b | Reserved Always reads 1000b. |
5:4 | SPARE[1:0] | R/W | 01b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
3:0 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SPARE[15:0] | R/W | 0000000000000000b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | SPARE[7:0] | R/W | 00000000b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SPARE[15:0] | R/W | 0000000000000000b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_MAP2_CRC_VALUE[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_MAP2_CRC_VALUE[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | REG_MAP2_CRC_VALUE[15:0] | R/W | 0000000000000000b | Register map CRC value for section 2 Register map CRC value for section 2. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_MAP3_CRC_EN | RESERVED | ||||||
R/W-0b | R-000000000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TDACB_VALUE[2:0] | ||||||
R-000000000000b | R/W-000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | REG_MAP3_CRC_EN | R/W | 0b | Register map section 3 CRC enable Enables the register map CRC for section 3 (register address space from C0h to E3h). 0b = Disabled 1b = Enabled |
14:3 | RESERVED | R | 000000000000b | Reserved Always reads 000000000000b. |
2:0 | TDACB_VALUE[2:0] | R/W | 000b | Test DAC B output value Selects the output value of Test DAC B. 000b = 1 x VREFB/40 001b = 2 x VREFB/40 010b = 4 x VREFB/40 011b = 9 x VREFB/40 100b = 18 x VREFB/40 101b = 36 x VREFB/40 110b = –4 x VREFB/40 111b = –9 x VREFB/40 |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SPARE[2:0] | GPIO1B_FMT | GPIO0B_FMT | GPIO1B_DIR | GPIO0B_DIR | ||
R-1b | R/W-000b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO1B_PWM_TB[1:0] | GPIO0B_PWM_TB[1:0] | SPARE[1:0] | GPO1B_DAT | GPO0B_DAT | |||
R/W-00b | R/W-00b | R/W-00b | R/W-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 1b | Reserved Always reads 1b. |
14:12 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
11 | GPIO1B_FMT | R/W | 0b | GPIO1B format Configures GPIO1B for static input and output levels or for PWM input levels. 0b = When GPIO1B is configured as a digital input: Logic levels are based on static input levels. When GPIO1B is configured as a digital output: Output with static output levels. 1b = When GPIO1B is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO1B is configured as a digital output: Output with static output levels. GPIO1B does not have PWM output capability. |
10 | GPIO0B_FMT | R/W | 0b | GPIO0B format Configures GPIO0B for static input and output levels or for PWM input levels. 0b = When GPIO0B is configured as a digital input: Logic levels are based on static input levels. When GPIO0B is configured as a digital output: Output with static output levels. 1b = When GPIO0B is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO0B is configured as a digital output: Output with static output levels. GPIO0B does not have PWM output capability. |
9 | GPIO1B_DIR | R/W | 0b | GPIO1B direction Configures GPIO1B as a digital input or digital output. 0b = Digital input 1b = Digital output |
8 | GPIO0B_DIR | R/W | 0b | GPIO0B direction Configures GPIO0B as a digital input or digital output. 0b = Digital input 1b = Digital output |
7:6 | GPIO1B_PWM_TB[1:0] | R/W | 00b | GPIO1B PWM time base selection Selects the time base used for the PWM encoder when GPIO1B is configured as a digital input. 00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz) 01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz) 10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz) 11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz) |
5:4 | GPIO0B_PWM_TB[1:0] | R/W | 00b | GPIO0B PWM time base selection Selects the time base used for the PWM encoder when GPIO0B is configured as a digital input. 00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz) 01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz) 10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz) 11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz) |
3:2 | SPARE[1:0] | R/W | 00b | Spare bits Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect. |
1 | GPO1B_DAT | R/W | 0b | GPIO1B output data Output value of GPIO1B when configured as an output. Bit setting has not effect when GPIO1B is configured as a digital input. 0b = Low 1b = High |
0 | GPO0B_DAT | R/W | 0b | GPIO0B output data Output value of GPIO0B when configured as an output. Bit setting has not effect when GPIO0B is configured as a digital input. 0b = Low 1b = High |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CONV_MODE1B | OSR1B[2:0] | |||||
R-0000b | R/W-0b | R/W-100b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GC1B_EN | GC1B_DELAY[2:0] | |||||
R-0000b | R/W-0b | R/W-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
11 | CONV_MODE1B | R/W | 0b | Conversion mode selection Selects the conversion mode for ADC1B. 0b = Continuous-conversion mode 1b = Single-shot conversion mode |
10:8 | OSR1B[2:0] | R/W | 100b | Oversampling ratio selection Selects the oversampling ratio for ADC1B. The data rate calculates to fMOD / OSR. 000b = 64 001b = 128 010b = 256 011b = 512 100b = 1024 101b = 2048 110b = 4096 111b = 8192 |
7:4 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
3 | GC1B_EN | R/W | 0b | Global-chop mode enable Enables the global-chop mode for ADC1B. 0b = Disabled 1b = Enabled |
2:0 | GC1B_DELAY[2:0] | R/W | 000b | Global-chop mode delay time selection Selects the delay time in global-chop mode for ADC1B. 000b = 2 x tMOD 001b = 4 x tMOD 010b = 8 x tMOD 011b = 16 x tMOD 100b = 32 x tMOD 101b = 64 x tMOD 110b = 128 x tMOD 111b = 256 x tMOD |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ADC1B_EN | RESERVED | GAIN1B[1:0] | MUX1B[1:0] | ||||
R/W-1b | R-000b | R/W-00b | R/W-00b | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OWD1B_SOURCE_MUX | OWD1B_SINK_MUX | OWD1B_SOURCE_VALUE[1:0] | OWD1B_SINK_VALUE[1:0] | |||
R-00b | R/W-0b | R/W-1b | R/W-00b | R/W-00b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | ADC1B_EN | R/W | 1b | ADC1B enable Enables ADC1B. The conversion data of ADC1B reset to 000000h and the conversion counter CONV1B_COUNT[1:0] resets to 00b when ADC1B is disabled or when the device is put in standby or power-down mode.. 0b = Disabled 1b = Enabled |
14:12 | RESERVED | R | 000b | Reserved Always reads 000b. |
11:10 | GAIN1B[1:0] | R/W | 00b | ADC1B gain selection Selects the gain (FSR = full scale range) of ADC1B. Gains 16 and 32 are digital gains using analog gain = 8. 00b = 4 01b = 8 10b = 16 11b = 32 |
9:8 | MUX1B[1:0] | R/W | 00b | ADC1B multiplexer channel selection Selects the multiplexer channel for ADC1B. 00b = AINp = CPB, AINn = CNB 01b = AINp = CNB, AINn = CPB 10b = Internal short to AGNDB. Analog inputs CPB, CNB disconnected from ADC1B. 11b = Test DAC A output |
7:6 | RESERVED | R | 00b | Reserved Always reads 00b. |
5 | OWD1B_SOURCE_MUX | R/W | 0b | ADC1B current source multiplexer selection Selects the multiplexer channel for the ADC1B current source. 0b = CPB 1b = CNB |
4 | OWD1B_SINK_MUX | R/W | 1b | ADC1B current sink multiplexer selection Selects the multiplexer channel for the ADC1B current sink. 0b = CPB 1b = CNB |
3:2 | OWD1B_SOURCE_VALUE[1:0] | R/W | 00b | ADC1B current source value selection Selects the current value for the ADC1B current source. 00b = Off 01b = 4 µA 10b = 40 µA 11b = 240 µA |
1:0 | OWD1B_SINK_VALUE[1:0] | R/W | 00b | ADC1B current sink value selection Selects the current value for the ADC1B current sink. 00b = Off 01b = 4 µA 10b = 40 µA 11b = 240 µA |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL1B[23:8] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL1B[23:8] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL1B[23:8] | R/W | 0000000000000000b | ADC1B offset calibration bits [23:8] Value provided in two's complement format. LSB size = (2 x VREFB) / (GAIN1B x 224) |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL1B[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL1B[7:0] | R/W | 00000000b | ADC1B offset calibration bits [7:0] Value provided in two's complement format. LSB size = (2 x VREFB) / (GAIN1B x 224) |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL1B[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL1B[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL1B[15:0] | R/W | 0000000000000000b | ADC1B gain calibration bits [15:0] Value provided in two's complement format. LSB size = 1/216 = 0.000015 Mapping: 0111111111111111b = 1.499985 0000000000000001b = 1.000015 0000000000000000b = 1 1111111111111111b = 0.999985 1000000000000000b = 0.5 |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCCB_EN | OCCB_POL | RESERVED | OCCB_NUM[4:0] | ||||
R/W-0b | R/W-0b | R/W-0b | R/W-00000b | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | OCCB_EN | R/W | 0b | ADC1B overcurrent comparator enable Enables the digital fast filter and digital comparator on ADC1B. ADC1B must be enabled to use the overcurrent comparator. The fast filter is not affected by the STARTB and STOPB bits. 0b = Disabled 1b = Enabled |
14 | OCCB_POL | R/W | 0b | OCCB pin polarity selection Selects the polarity of the OCCB pin. The actual output behavior of the GPIO4/OCCB pin, when configured as OCCB output in the GPIO4_SRC bit, depends on the GPIO4_FMT setting. An OCCB fault is active when any of the OCCB_HTn or OCCB_LTn bits are active. 0b = Active low. In case of a fault a logic low level is driven. 1b = Active high. In case of a fault a logic high level is driven. |
13 | RESERVED | R/W | 0b | Reserved Always write 0b. |
12:8 | OCCB_NUM[4:0] | R/W | 00000b | ADC1B overcurrent comparator deglitch filter selection Selects the number of conversions the output of the ADC1B digital fast filter must exceed the set high or low thresholds to trip the OCCB_HTn or OCCB_LTn comparator output. The fast filter path uses a SINC3 filter with a fixed OSR = 64. The counter starts again whenever the digital fast filter output falls below the threshold, means there is no hysteresis. 00000b = 1 00001b = 2 00010b = 3 00011b = 4 00100b = 5 00101b = 6 00110b = 7 00111b = 8 01000b = 9 01001b = 10 01010b = 12 01011b = 14 01100b = 16 01101b = 18 01110b = 20 01111b = 22 10000b = 24 10001b = 26 10010b = 28 10011b = 32 10100b = 40 10101b = 48 10110b = 56 10111b = 64 11000b = 72 11001b = 80 11010b = 88 11011b = 96 11100b = 104 11101b = 112 11110b = 120 11111b = 128 |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCCB_HIGH_TH[15:0] | |||||||
R/W-0111111111111111b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCCB_HIGH_TH[15:0] | |||||||
R/W-0111111111111111b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCCB_HIGH_TH[15:0] | R/W | 0111111111111111b | ADC1B overcurrent comparator high threshold bits [15:0] Value provided in two's complement format. LSB size = (2 x VREFB) / (GAIN1B x 216) Values larger than the high threshold trigger an OCCB_HTn event. Setting the value to +FS (= 7FFFh) disables the high threshold detection. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCCB_LOW_TH[15:0] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCCB_LOW_TH[15:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCCB_LOW_TH[15:0] | R/W | 1000000000000000b | ADC1B overcurrent comparator low threshold bits [15:0] Value provided in two's complement format. LSB size = (2 x VREFB) / (GAIN1B x 216) Values smaller than the low threshold trigger an OCCB_LTn event. Setting the value to –FS (= 8000h) disables the low threshold detection. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[15:0] | |||||||
R/W-0101010101010101b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[15:0] | |||||||
R/W-0101010101010101b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SPARE[15:0] | R/W | 0101010101010101b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SPARE[6:0] | ||||||
R-00000b | R/W-0000001b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[6:0] | RESERVED | ||||||
R/W-0000001b | R-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:11 | RESERVED | R | 00000b | Reserved Always reads 00000b. |
10:4 | SPARE[6:0] | R/W | 0000001b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
3:0 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[1:0] | RESERVED | SPARE[2:0] | |||||
R/W-00b | R-000b | R/W-000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[1:0] | ||||||
R-000000b | R/W-00b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | SPARE[1:0] | R/W | 00b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
13:11 | RESERVED | R | 000b | Reserved Always reads 00b. |
10:8 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
7:2 | RESERVED | R | 000000b | Reserved Always reads 000000b. |
1:0 | SPARE[1:0] | R/W | 00b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
7:0 | SPARE[7:0] | R/W | 00000000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SPARE[15:0] | R/W | 0000000000000000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SPARE[15:0] | R/W | 0000000000000000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-00000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 00000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-00001b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 00001b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-00010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 00010b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-00011b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 00011b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-00100b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 00100b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-00101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 00101b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-00110b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 00110b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-00111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 00111b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-01000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 01000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-01001b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 01001b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-01010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 01010b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-01011b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 01011b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-01100b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 01100b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-01101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 01101b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-01110b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 01110b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[2:0] | RESERVED | ||||||
R/W-000b | R-00000000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[4:0] | ||||||
R-00000000b | R/W-01111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | SPARE[2:0] | R/W | 000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
12:5 | RESERVED | R | 00000000b | Reserved Always reads 00000000b. |
4:0 | SPARE[4:0] | R/W | 01111b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SPARE[1:0] | RESERVED | |||||
R-0000b | R/W-00b | R-1000b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPARE[1:0] | RESERVED | |||||
R-1000b | R/W-01b | R-0000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
11:10 | SPARE[1:0] | R/W | 00b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
9:6 | RESERVED | R | 1000b | Reserved Always reads 1000b. |
5:4 | SPARE[1:0] | R/W | 01b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
3:0 | RESERVED | R | 0000b | Reserved Always reads 0000b. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SPARE[15:0] | R/W | 0000000000000000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | SPARE[7:0] | R/W | 00000000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 0x00. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPARE[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | SPARE[15:0] | R/W | 0000000000000000b | Spare bits Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_MAP3_CRC_VALUE[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_MAP3_CRC_VALUE[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | REG_MAP3_CRC_VALUE[15:0] | R/W | 0000000000000000b | Register map CRC value for section 3 Register map CRC value for section 3. |