JAJSPC7A December   2022  – August 2023 ADS131B23

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Offset Drift Measurement
    2. 7.2 Gain Drift Measurement
    3. 7.3 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Naming Conventions
      2. 8.3.2 Precision Voltage References (REFA, REFB)
      3. 8.3.3 Clocking (MCLK, OSCM, OSCD)
      4. 8.3.4 ADC1y
        1. 8.3.4.1 ADC1y Input Multiplexer
        2. 8.3.4.2 ADC1y Programmable Gain Amplifier (PGA)
        3. 8.3.4.3 ADC1y ΔΣ Modulator
        4. 8.3.4.4 ADC1y Digital Filter
        5. 8.3.4.5 ADC1y Offset and Gain Calibration
        6. 8.3.4.6 ADC1y Conversion Data
      5. 8.3.5 ADC2y
        1. 8.3.5.1 ADC2y Input Multiplexer
        2. 8.3.5.2 ADC2y Programmable Gain Amplifier (PGA)
        3. 8.3.5.3 ADC2y ΔΣ Modulator
        4. 8.3.5.4 ADC2y Digital Filter
        5. 8.3.5.5 ADC2y Offset and Gain Calibration
        6. 8.3.5.6 ADC2y Sequencer
        7. 8.3.5.7 VCMy Buffers
        8. 8.3.5.8 ADC2y Measurement Configurations
        9. 8.3.5.9 ADC2y Conversion Data
      6. 8.3.6 General-Purpose Digital Inputs and Outputs (GPIO0 to GPIO4)
        1. 8.3.6.1 GPIOx PWM Output Configuration
        2. 8.3.6.2 GPIOx PWM Input Readback
      7. 8.3.7 General-Purpose Digital Inputs and Outputs (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
      8. 8.3.8 Monitors and Diagnostics
        1. 8.3.8.1  Supply Monitors
        2. 8.3.8.2  Clock Monitors
        3. 8.3.8.3  Digital Monitors
          1. 8.3.8.3.1 Register Map CRC
          2. 8.3.8.3.2 Memory Map CRC
          3. 8.3.8.3.3 GPIO Readback
        4. 8.3.8.4  Communication Monitors
        5. 8.3.8.5  Fault Flags and Fault Masking
        6. 8.3.8.6  FAULT Pin
        7. 8.3.8.7  Diagnostics and Diagnostic Procedure
        8. 8.3.8.8  Indicators
        9. 8.3.8.9  Conversion and Sequence Counters
        10. 8.3.8.10 Supply Voltage Readback
        11. 8.3.8.11 Temperature Sensor (TSA)
        12. 8.3.8.12 Test DACs (TDACA, TDACB)
        13. 8.3.8.13 Open-Wire Detection
        14. 8.3.8.14 Missing Host Detection and MHD Pin
        15. 8.3.8.15 Overcurrent Comparators (OCCA, OCCB)
          1. 8.3.8.15.1 OCCA and OCCB Pins
          2. 8.3.8.15.2 Overcurrent Indication Response Time
    4. 8.4 デバイスの機能モード
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 RESETn Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Active Mode
        2. 8.4.2.2 Standby Mode
        3. 8.4.2.3 Power-Down Mode
      3. 8.4.3 ADC Conversion Modes
        1. 8.4.3.1 ADC1y Conversion Modes
          1. 8.4.3.1.1 Continuous-Conversion Mode
          2. 8.4.3.1.2 Single-Shot Conversion Mode
          3. 8.4.3.1.3 Global-Chop Mode
            1. 8.4.3.1.3.1 Overcurrent Indication Response Time in Global-Chop Mode
        2. 8.4.3.2 ADC2y Sequencer Operation and Sequence Modes
          1. 8.4.3.2.1 Continuous Sequence Mode
          2. 8.4.3.2.2 Single-Shot Sequence Mode
          3. 8.4.3.2.3 Synchronized Single-Shot Sequence Mode Based on ADC1y Conversion Starts
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Serial Interface Signals
          1. 8.5.1.1.1 Chip Select (CSn)
          2. 8.5.1.1.2 Serial Data Clock (SCLK)
          3. 8.5.1.1.3 Serial Data Input (SDI)
          4. 8.5.1.1.4 Serial Data Output (SDO)
          5. 8.5.1.1.5 Data Ready (DRDYn)
        2. 8.5.1.2 Serial Interface Communication Structure
          1. 8.5.1.2.1 SPI Communication Frames
          2. 8.5.1.2.2 SPI Communication Words
          3. 8.5.1.2.3 STATUS Word
          4. 8.5.1.2.4 Communication Cyclic Redundancy Check (CRC)
          5. 8.5.1.2.5 Commands
            1. 8.5.1.2.5.1 NULL (0000 0000 0000 0000b)
            2. 8.5.1.2.5.2 RESET (0000 0000 0001 0001b)
            3. 8.5.1.2.5.3 LOCK (0000 0101 0101 0101b)
            4. 8.5.1.2.5.4 UNLOCK (0000 0110 0101 0101b)
            5. 8.5.1.2.5.5 WREG (011a aaaa aaa0 0nnnb)
            6. 8.5.1.2.5.6 RREG (101a aaaa aaan nnnnb)
          6. 8.5.1.2.6 SCLK Counter
          7. 8.5.1.2.7 SPI Timeout
          8. 8.5.1.2.8 Reading ADC1A, ADC1B, and ADC2A Conversion Data
          9. 8.5.1.2.9 DRDYn Pin Behavior
    6. 8.6 Register Map
      1. 8.6.1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Minimum Interface Connections
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current-Shunt Measurement
        2. 9.2.2.2 Battery-Pack Voltage Measurement
        3. 9.2.2.3 Shunt Temperature Measurement
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Options
        1. 9.3.1.1 Single Unregulated External 4-V to 16-V Supply (3.3-V Digital I/O Levels)
        2. 9.3.1.2 Single Regulated External 3.3-V Supply (3.3-V Digital IO Levels)
        3. 9.3.1.3 Single Regulated External 5-V Supply (5-V Digital I/O Levels)
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントのサポート
      1. 10.1.1 関連資料
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.8 Monitors and Diagnostics

The ADS131B23 integrates many monitor and diagnostic circuits to aid in the design of functional safety systems. Monitors detect faults in the device, such as a supply undervoltage condition, whereas diagnostics detect faults within the monitoring circuit to check if the monitor is still working as intended.

Table 8-14 provides an overview of all available monitors and diagnostics. Most monitors can be enabled or disabled as required using a dedicated monitor enable bit. If a monitor detects a fault, the according low-active fault flag is set to 0b. Except for the communication-related monitor fault flags, the fault flags must be cleared to 1b by the host after the fault condition is removed. The communication-related monitor fault flags reset to 1b automatically in the SPI frame following a frame where no communication fault occurred.

The monitors that have a dedicated diagnostic circuit to check the integrity of the monitor show the respective diagnostic enable bit in Table 8-14.

The monitors have individual fault response times, which is the time from fault occurrence to fault flag indication, as specified in the Electrical Characteristics table.

Table 8-14 Monitor and Diagnostic Overview
MONITOR NAME MONITOR ENABLE BIT MONITOR FAULT FLAG DIAGNOSTIC ENABLE BIT FAULT FLAG REGISTER LOCATION
SUPPLY MONITORS AND DIAGNOSTICS
Reset N/A RESETn N/A STATUS_MSB
AVDD overvoltage AVDD_OV_EN AVDD_OVn AVDD_OV_DIAG_EN SUPPLY_STATUS
AVDD undervoltage AVDD_UV_EN AVDD_UVn AVDD_UV_DIAG_EN SUPPLY_STATUS
IOVDD overvoltage IOVDD_OV_EN IOVDD_OVn IOVDD_OV_DIAG_EN SUPPLY_STATUS
IOVDD undervoltage IOVDD_UV_EN IOVDD_UVn IOVDD_UV_DIAG_EN SUPPLY_STATUS
DVDD overvoltage DVDD_OV_EN DVDD_OVn DVDD_OV_DIAG_EN SUPPLY_STATUS
DVDD undervoltage DVDD_UV_EN DVDD_UVn DVDD_UV_DIAG_EN SUPPLY_STATUS
AVDD oscillation AVDD_OSC_EN AVDD_OSCn AVDD_OSC_DIAG_EN SUPPLY_STATUS
IOVDD oscillation IOVDD_OSC_EN IOVDD_OSCn IOVDD_OSC_DIAG_EN SUPPLY_STATUS
DVDD oscillation DVDD_OSC_EN DVDD_OSCn DVDD_OSC_DIAG_EN SUPPLY_STATUS
AVDD LDO overtemperature warning AVDD_OTW_EN AVDD_OTWn N/A SUPPLY_STATUS
IOVDD LDO overtemperature warning IOVDD_OTW_EN IOVDD_OTWn N/A SUPPLY_STATUS
AVDD LDO output current limit AVDD_CL_EN AVDD_CLn N/A SUPPLY_STATUS
IOVDD LDO output current limit IOVDD_CL_EN IOVDD_CLn N/A SUPPLY_STATUS
AGNDA pin disconnect AGNDA_DISC_EN AGNDA_DISCn AGNDA_DISC_DIAG_EN SUPPLY_STATUS
AGNDB pin disconnect AGNDB_DISC_EN AGNDB_DISCn AGNDB_DISC_DIAG_EN SUPPLY_STATUS
DGND pin disconnect DGND_DISC_EN DGND_DISCn DGND_DISC_DIAG_EN SUPPLY_STATUS
CLOCK MONITORS AND DIAGNOSTICS
Main clock frequency MCLK_MON_EN MCLK_FAULTn MCLK_HI_DIAG_EN, MCLK_LO_DIAG_EN CLOCK_STATUS
Diagnostic oscillator watchdog OSCD_WD_EN OSCD_WDn OSCD_WD_DIAG_EN CLOCK_STATUS
Main clock watchdog MCLK_WD_EN MCLK_WDn MCLK_WD_DIAG_EN CLOCK_STATUS
DIGITAL MONITORS AND DIAGNOSTICS
Register map section 1 CRC REG_MAP1_CRC_EN REG_MAP1_CRC_FAULTn N/A DIGITAL_STATUS
Register map section 2 CRC REG_MAP2_CRC_EN REG_MAP2_CRC_FAULTn N/A DIGITAL_STATUS
Register map section 3 CRC REG_MAP3_CRC_EN REG_MAP3_CRC_FAULTn N/A DIGITAL_STATUS
Memory map CRC N/A MEM_MAP_CRC_FAULTn MEM_MAP_CRC_DIAG[1:0] DIGITAL_STATUS
GPIOA readback N/A N/A GPIOA_DIAG_EN GPIA_GPIB_DATA
GPIOB readback N/A N/A GPIOB_DIAG_EN GPIA_GPIB_DATA
GPIO readback N/A N/A GPIO_DIAG_EN GPI_DATA
COMMUNICATION MONITORS AND DIAGNOSTICS
SPI CRC N/A SPI_CRC_FAULTn N/A STATUS_MSB
SPI timeout TIMEOUT_EN SPI_TIMEOUTn N/A STATUS_MSB
SCLK counter SCLK_COUNTER_EN SCLK_COUNT_FAULTn N/A STATUS_MSB
Register access N/A REG_ACCESS_FAULTn N/A STATUS_MSB

In addition to the monitors that detect faults in the device, the ADS131B23 also provides the indicators shown in Table 8-15, which provides feedback about the device state or behavior.

Table 8-15 Indicator Overview
INDICATOR NAME INDICATOR STATUS BIT STATUS BIT REGISTER LOCATION
Command response COMMAND_RESPONSE[3:0] STATUS_MSB
Lock state LOCK STATUS_MSB
Clock source CLOCK STATUS_MSB
Operating mode MODE STATUS_MSB
ADC2A sequence active SEQ2A_ACTIVE STATUS_LSB
OTP bank OTB_BANK DIGITAL_STATUS

Lastly, the device provides the conversion and sequence counters shown in Table 8-16 for the individual ADCs.

Table 8-16 Conversion and Sequence Counter Overview
COUNTER NAME COUNTER BITS COUNTER BITS REGISTER LOCATION
ADC1A conversion counter CONV1A_COUNT[1:0] STATUS_LSB
ADC1B conversion counter CONV1B_COUNT[1:0] STATUS_LSB
ADC2A sequencer counter SEQ2A_COUNT[1:0] STATUS_LSB

Besides the monitors, indicators, and counters mentioned in the previous tables, the ADS131B23 offers additional means to check the integrity of the device, such as:

  • Power-supply voltage readback using ADC2A
  • A temperature sensor, TSA
  • Two test DACs, TDACA and TDACB
  • Open-wire detection current sources and sinks on every ADC