JAJSPC7A December   2022  – August 2023 ADS131B23

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Offset Drift Measurement
    2. 7.2 Gain Drift Measurement
    3. 7.3 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Naming Conventions
      2. 8.3.2 Precision Voltage References (REFA, REFB)
      3. 8.3.3 Clocking (MCLK, OSCM, OSCD)
      4. 8.3.4 ADC1y
        1. 8.3.4.1 ADC1y Input Multiplexer
        2. 8.3.4.2 ADC1y Programmable Gain Amplifier (PGA)
        3. 8.3.4.3 ADC1y ΔΣ Modulator
        4. 8.3.4.4 ADC1y Digital Filter
        5. 8.3.4.5 ADC1y Offset and Gain Calibration
        6. 8.3.4.6 ADC1y Conversion Data
      5. 8.3.5 ADC2y
        1. 8.3.5.1 ADC2y Input Multiplexer
        2. 8.3.5.2 ADC2y Programmable Gain Amplifier (PGA)
        3. 8.3.5.3 ADC2y ΔΣ Modulator
        4. 8.3.5.4 ADC2y Digital Filter
        5. 8.3.5.5 ADC2y Offset and Gain Calibration
        6. 8.3.5.6 ADC2y Sequencer
        7. 8.3.5.7 VCMy Buffers
        8. 8.3.5.8 ADC2y Measurement Configurations
        9. 8.3.5.9 ADC2y Conversion Data
      6. 8.3.6 General-Purpose Digital Inputs and Outputs (GPIO0 to GPIO4)
        1. 8.3.6.1 GPIOx PWM Output Configuration
        2. 8.3.6.2 GPIOx PWM Input Readback
      7. 8.3.7 General-Purpose Digital Inputs and Outputs (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
      8. 8.3.8 Monitors and Diagnostics
        1. 8.3.8.1  Supply Monitors
        2. 8.3.8.2  Clock Monitors
        3. 8.3.8.3  Digital Monitors
          1. 8.3.8.3.1 Register Map CRC
          2. 8.3.8.3.2 Memory Map CRC
          3. 8.3.8.3.3 GPIO Readback
        4. 8.3.8.4  Communication Monitors
        5. 8.3.8.5  Fault Flags and Fault Masking
        6. 8.3.8.6  FAULT Pin
        7. 8.3.8.7  Diagnostics and Diagnostic Procedure
        8. 8.3.8.8  Indicators
        9. 8.3.8.9  Conversion and Sequence Counters
        10. 8.3.8.10 Supply Voltage Readback
        11. 8.3.8.11 Temperature Sensor (TSA)
        12. 8.3.8.12 Test DACs (TDACA, TDACB)
        13. 8.3.8.13 Open-Wire Detection
        14. 8.3.8.14 Missing Host Detection and MHD Pin
        15. 8.3.8.15 Overcurrent Comparators (OCCA, OCCB)
          1. 8.3.8.15.1 OCCA and OCCB Pins
          2. 8.3.8.15.2 Overcurrent Indication Response Time
    4. 8.4 デバイスの機能モード
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 RESETn Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Active Mode
        2. 8.4.2.2 Standby Mode
        3. 8.4.2.3 Power-Down Mode
      3. 8.4.3 ADC Conversion Modes
        1. 8.4.3.1 ADC1y Conversion Modes
          1. 8.4.3.1.1 Continuous-Conversion Mode
          2. 8.4.3.1.2 Single-Shot Conversion Mode
          3. 8.4.3.1.3 Global-Chop Mode
            1. 8.4.3.1.3.1 Overcurrent Indication Response Time in Global-Chop Mode
        2. 8.4.3.2 ADC2y Sequencer Operation and Sequence Modes
          1. 8.4.3.2.1 Continuous Sequence Mode
          2. 8.4.3.2.2 Single-Shot Sequence Mode
          3. 8.4.3.2.3 Synchronized Single-Shot Sequence Mode Based on ADC1y Conversion Starts
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Serial Interface Signals
          1. 8.5.1.1.1 Chip Select (CSn)
          2. 8.5.1.1.2 Serial Data Clock (SCLK)
          3. 8.5.1.1.3 Serial Data Input (SDI)
          4. 8.5.1.1.4 Serial Data Output (SDO)
          5. 8.5.1.1.5 Data Ready (DRDYn)
        2. 8.5.1.2 Serial Interface Communication Structure
          1. 8.5.1.2.1 SPI Communication Frames
          2. 8.5.1.2.2 SPI Communication Words
          3. 8.5.1.2.3 STATUS Word
          4. 8.5.1.2.4 Communication Cyclic Redundancy Check (CRC)
          5. 8.5.1.2.5 Commands
            1. 8.5.1.2.5.1 NULL (0000 0000 0000 0000b)
            2. 8.5.1.2.5.2 RESET (0000 0000 0001 0001b)
            3. 8.5.1.2.5.3 LOCK (0000 0101 0101 0101b)
            4. 8.5.1.2.5.4 UNLOCK (0000 0110 0101 0101b)
            5. 8.5.1.2.5.5 WREG (011a aaaa aaa0 0nnnb)
            6. 8.5.1.2.5.6 RREG (101a aaaa aaan nnnnb)
          6. 8.5.1.2.6 SCLK Counter
          7. 8.5.1.2.7 SPI Timeout
          8. 8.5.1.2.8 Reading ADC1A, ADC1B, and ADC2A Conversion Data
          9. 8.5.1.2.9 DRDYn Pin Behavior
    6. 8.6 Register Map
      1. 8.6.1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Minimum Interface Connections
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current-Shunt Measurement
        2. 9.2.2.2 Battery-Pack Voltage Measurement
        3. 9.2.2.3 Shunt Temperature Measurement
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Options
        1. 9.3.1.1 Single Unregulated External 4-V to 16-V Supply (3.3-V Digital I/O Levels)
        2. 9.3.1.2 Single Regulated External 3.3-V Supply (3.3-V Digital IO Levels)
        3. 9.3.1.3 Single Regulated External 5-V Supply (5-V Digital I/O Levels)
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントのサポート
      1. 10.1.1 関連資料
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.5.1.2.2 SPI Communication Words

An SPI communication frame of the ADS131B23 is made of multiple words. The word size is configurable as either 24 bits, or 32 bits using the WORD_LENGTH bit in the DEVICE_CFG register. The content within each word is always most significant bit (MSB) aligned and least significant bit (LSB) padded with zeros to accommodate 24-bit or 32-bit word sizes. Table 8-22 provides an overview of all available word types and the actual unpadded data length of the respective content.

Table 8-22 Unpadded Data Length of Individual Word Types
DIRECTION WORD TYPE UNPADDED DATA LENGTH
SDI Command 16 bits
SDI Command CRC 16 bits
SDI Register data for WREG command 16 bits
SDI Register data CRC for WREG command 16 bits
SDO STATUS 24 bits
SDO ADC1A and ADC1B conversion data 24 bits
SDO Register data for RREG command 16 bits register data + 8 bits register address
SDO Output CRC 16 bits

Figure 8-29 and Figure 8-30 show the bit alignments and zero padding within the individual words for a WREG and RREG command, respectively.

GUID-20211220-SS0I-GFZH-8J1K-RL3W3PBW6CW0-low.svg Figure 8-29 Bit Alignment, 24-Bit Word Size, WREG Command
GUID-20211220-SS0I-NKKX-S8N3-PDWJG0D6ZFSB-low.svg Figure 8-30 Bit Alignment, 24-Bit Word Size, RREG Command