The ADS131B24-Q1 register map spans across the address space from 00h to FEh
and is divided into four general sections:
- Section 0 (address space: 00h
to 2Fh): Only
includes read-only bits (such as ID, status, GPIO input data, ADC2y
conversion data, and the conversion and sequence control bits)
- Section 1 (address space: 40h
to 7Eh): Includes global device configuration bits that are not specific to
section A or B of the device
- Section 2 (address space: 80h
to BEh): Includes device configuration bits that are specific to section
A
- Section 3 (address space: C0h
to FEh): Includes device configuration bits that are specific to section
B