JAJSML5A March   2022  – August 2022 ADS131M04-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. 8.3.7.1 Digital Filter Implementation
          1. 8.3.7.1.1 Fast-Settling Filter
          2. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.7.2 Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0101 0101)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 ADS131M04-Q1 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 CAP Pin Behavior
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 ADS131M04-Q1 Registers

Table 8-12 lists the ADS131M04-Q1 registers. All register offset addresses not listed in Table 8-12 should be considered as reserved locations and the register contents should not be modified.

Table 8-12 Register Map
ADDRESS REGISTER RESET VALUE BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DEVICE SETTINGS AND INDICATORS (Read-Only Registers)
00h ID 24xxh RESERVED CHANCNT[3:0]
RESERVED
01h STATUS 0500h LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0]
RESERVED DRDY3 DRDY2 DRDY1 DRDY0
GLOBAL SETTINGS ACROSS CHANNELS
02h MODE 0510h RESERVED REGCRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0]
RESERVED TIMEOUT DRDY_SEL[1:0] DRDY_HiZ DRDY_FMT
03h CLOCK 0F0Eh RESERVED CH3_EN CH2_EN CH1_EN CH0_EN
RESERVED TBM OSR[2:0] PWR[1:0]
04h GAIN1 0000h RESERVED PGAGAIN3[2:0] RESERVED PGAGAIN2[2:0]
RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0]
06h CFG 0600h RESERVED GC_DLY[3:0] GC_EN
CD_ALLCH CD_NUM[2:0] CD_LEN[2:0] CD_EN
07h THRSHLD_MSB 0000h CD_TH_MSB[15:8]
CD_TH_MSB[7:0]
08h THRSHLD_LSB 0000h CD_TH_LSB[7:0]
RESERVED DCBLOCK[3:0]
CHANNEL-SPECIFIC SETTINGS
09h CH0_CFG 0000h PHASE0[9:2]
PHASE0[1:0] RESERVED DCBLK0_DIS0 MUX0[1:0]
0Ah CH0_OCAL_MSB 0000h OCAL0_MSB[15:8]
OCAL0_MSB[7:0]
0Bh CH0_OCAL_LSB 0000h OCAL0_LSB[7:0]
RESERVED
0Ch CH0_GCAL_MSB 8000h GCAL0_MSB[15:8]
GCAL0_MSB[7:0]
0Dh CH0_GCAL_LSB 0000h GCAL0_LSB[7:0]
RESERVED
0Eh CH1_CFG 0000h PHASE1[9:2]
PHASE1[1:0] RESERVED DCBLK1_DIS0 MUX1[1:0]
0Fh CH1_OCAL_MSB 0000h OCAL1_MSB[15:8]
OCAL1_MSB[7:0]
10h CH1_OCAL_LSB 0000h OCAL1_LSB[7:0]
RESERVED
11h CH1_GCAL_MSB 8000h GCAL1_MSB[15:8]
GCAL1_MSB[7:0]
12h CH1_GCAL_LSB 0000h GCAL1_LSB[7:0]
RESERVED
13h CH2_CFG 0000h PHASE2[9:2]
PHASE2[1:0] RESERVED DCBLK2_DIS0 MUX2[1:0]
14h CH2_OCAL_MSB 0000h OCAL2_MSB[15:8]
OCAL2_MSB[7:0]
15h CH2_OCAL_LSB 0000h OCAL2_LSB[7:0]
RESERVED
16h CH2_GCAL_MSB 8000h GCAL2_MSB[15:8]
GCAL2_MSB[7:0]
17h CH2_GCAL_LSB 0000h GCAL2_LSB[7:0]
RESERVED
18h CH3_CFG 0000h PHASE3[9:2]
PHASE3[1:0] RESERVED DCBLK3_DIS0 MUX3[1:0]
19h CH3_OCAL_MSB 0000h OCAL3_MSB[15:8]
OCAL3_MSB[7:0]
1Ah CH3_OCAL_LSB 0000h OCAL3_LSB[7:0]
RESERVED
1Bh CH3_GCAL_MSB 8000h GCAL3_MSB[15:8]
GCAL3_MSB[7:0]
1Ch CH3_GCAL_LSB 0000h GCAL3_LSB[7:0]
RESERVED
REGISTER MAP CRC AND RESERVED REGISTERS
3Eh REGMAP_CRC 0000h REG_CRC[15:8]
REG_CRC[7:0]
3Fh RESERVED 0000h RESERVED
RESERVED

Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for access types in this section.

Table 8-13 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.6.1 ID Register (Address = 0h) [reset = 24xxh]

The ID register is shown in Figure 8-26 and described in Table 8-14.

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Figure 8-26 ID Register
15 14 13 12 11 10 9 8
RESERVED CHANCNT[3:0]
R-0010b R-0100b
7 6 5 4 3 2 1 0
RESERVED
R-xxxxxxxxb
Table 8-14 ID Register Field Descriptions
Bit Field Type Reset Description
15:12 RESERVED R 0010b

Reserved

Always reads 0010b
11:8 CHANCNT[3:0] R 0100b

Channel count. Always reads 0100b.

7:0 RESERVED R xxxxxxxxb

Reserved

Values are subject to change without notice.

8.6.2 STATUS Register (Address = 1h) [reset = 0500h]

The STATUS register is shown in Figure 8-27 and described in Table 8-15.

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Figure 8-27 STATUS Register
15141312111098
LOCKF_RESYNCREG_MAPCRC_ERRCRC_TYPERESETWLENGTH[1:0]
R-0bR-0bR-0bR-0bR-0bR-1bR-01b
76543210
RESERVEDDRDY3DRDY2DRDY1DRDY0
R-0000bR-0bR-0bR-0bR-0b
Table 8-15 STATUS Register Field Descriptions
BitFieldTypeResetDescription
15LOCKR0b

SPI interface lock indicator

0b = Unlocked (default)

1b = Locked

14F_RESYNCR0b

ADC resynchronization indicator.

This bit is set each time the ADC resynchronizes.

0b = No resynchronization (default)

1b = Resynchronization occurred

13REG_MAPR0b

Register map CRC fault indicator

0b = No change in the register map CRC (default)

1b = Register map CRC changed

12CRC_ERRR0b

SPI input CRC error indicator

0b = No CRC error (default)

1b = Input CRC error occurred

11CRC_TYPER0b

CRC type

0b = 16-bit CCITT (default)

1b = 16-bit ANSI

10RESETR1b

Reset status

0b = Not reset

1b = Reset occurred (default)

9:8WLENGTH[1:0]R01b

Data word length

00b = 16 bits

01b = 24 bits (default)

10b = 32 bits; zero padding

11b = 32 bits; sign extension for 24-bit ADC data

7:4RESERVEDR0000b

Reserved

Always reads 0000b

3DRDY3R0b

Channel 3 ADC data available indicator

0b = No new data available

1b = New data are available

2DRDY2R0b

Channel 2 ADC data available indicator

0b = No new data available

1b = New data are available

1DRDY1R0b

Channel 1 ADC data available indicator

0b = No new data available

1b = New data are available

0DRDY0R0b

Channel 0 ADC data available indicator

0b = No new data available

1b = New data are available

8.6.3 MODE Register (Address = 2h) [reset = 0510h]

The MODE register is shown in Figure 8-28 and described in Table 8-16.

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Figure 8-28 MODE Register
15141312111098
RESERVEDREG_CRC_ENRX_CRC_ENCRC_TYPERESETWLENGTH[1:0]
R/W-00bR/W-0bR/W-0bR/W-0bR/W-1bR/W-01b
76543210
RESERVEDTIMEOUTDRDY_SEL[1:0]DRDY_HiZDRDY_FMT
R/W-000bR/W-1bR/W-00bR/W-0bR/W-0b
Table 8-16 MODE Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00b

Reserved

Always write 00b

13REG_CRC_ENR/W0b

Register map CRC enable

0b = Register CRC disabled (default)

1b = Register CRC enabled

12RX_CRC_ENR/W0b

SPI input CRC enable

0b = Disabled (default)

1b = Enabled

11CRC_TYPER/W0b

SPI input and output, register map CRC type

0b = 16-bit CCITT (default)

1b = 16-bit ANSI

10RESETR/W1b

Reset

Write 0b to clear this bit in the STATUS register

0b = No reset

1b = Reset occurred (default by definition)

9:8WLENGTH[1:0]R/W01b

Data word length selection

00b = 16 bits

01b = 24 bits (default)

10b = 32 bits; LSB zero padding

11b = 32 bits; MSB sign extension

7:5RESERVEDR/W000b

Reserved

Always write 000b

4TIMEOUTR/W1b

SPI Timeout enable

0b = Disabled

1b = Enabled (default)

3:2DRDY_SEL[1:0]R/W00b

DRDY pin signal source selection

00b = Most lagging enabled channel (default)

01b = Logic OR of all enabled channels

10b = Most leading enabled channel

11b = Most leading enabled channel

1DRDY_HiZR/W0b

DRDY pin state when conversion data are not available

0b = Logic high (default)

1b = High impedance

0DRDY_FMTR/W0b

DRDY signal format when conversion data are available

0b = Logic low (default)

1b = Low pulse with a fixed duration

8.6.4 CLOCK Register (Address = 3h) [reset = 0F0Eh]

The CLOCK register is shown in Figure 8-29 and described in Table 8-17.

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Figure 8-29 CLOCK Register
15141312111098
RESERVEDCH3_ENCH2_ENCH1_ENCH0_EN
R-0000bR/W-1bR/W-1bR/W-1bR/W-1b
76543210
RESERVED TBM OSR[2:0] PWR[1:0]
R/W-00b R/W-0bR/W-011bR/W-10b
Table 8-17 CLOCK Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0000b

Reserved

Always reads 0000b

11CH3_ENR/W1b

Channel 3 ADC enable

0b = Disabled

1b = Enabled (default)

10CH2_ENR/W1b

Channel 2 ADC enable

0b = Disabled

1b = Enabled (default)

9CH1_ENR/W1b

Channel 1 ADC enable

0b = Disabled

1b = Enabled (default)

8CH0_ENR/W1b

Channel 0 ADC enable

0b = Disabled

1b = Enabled (default)

7:6RESERVED R/W00b

Reserved

Always write 00b

5

TBM

 R/W 0b

Modulator oversampling ratio 64 selection (turbo mode)

0b = OSR set by bits 4:2 (that is, OSR[2:0])

1b = OSR of 64 is selected
4:2OSR[2:0]R/W011b

Modulator oversampling ratio selection

000b = 128

001b = 256

010b = 512

011b = 1024 (default)

100b = 2048

101b = 4096

110b = 8192

111b = 16384

1:0PWR[1:0]R/W10b

Power mode selection

00b = Very-low-power

01b = Low-power

10b = High-resolution (default)

11b = High-resolution

8.6.5 GAIN1 Register (Address = 4h) [reset = 0000h]

The GAIN1 register is shown in Figure 8-30 and described in Table 8-18.

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Figure 8-30 GAIN1 Register
15141312111098
RESERVEDPGAGAIN3[2:0]RESERVEDPGAGAIN2[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
76543210
RESERVEDPGAGAIN1[2:0]RESERVEDPGAGAIN0[2:0]
R/W-0bR/W-000bR/W-0bR/W-000b
Table 8-18 GAIN1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0b

Reserved

Always write 0b

14:12PGAGAIN3[2:0]R/W000b

PGA gain selection for channel 3

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

11RESERVEDR/W0b

Reserved

Always write 0b

10:8PGAGAIN2[2:0]R/W000b

PGA gain selection for channel 2

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

7RESERVEDR/W0b

Reserved

Always write 0b

6:4PGAGAIN1[2:0]R/W000b

PGA gain selection for channel 1

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

3RESERVEDR/W0b

Reserved

Always write 0b

2:0PGAGAIN0[2:0]R/W000b

PGA gain selection for channel 0

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

8.6.6 RESERVED Register (Address = 5h) [reset = 0000h]

The RESERVED register is shown in Figure 8-31 and described in Table 8-19.

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Figure 8-31 RESERVED Register
15141312111098
RESERVED
R/W-00000000b
76543210
RESERVED
R/W-00000000b
Table 8-19 RESERVED Register Field Descriptions
BitFieldTypeResetDescription
15:0RESERVEDR/W00000000
00000000b

Reserved

Always write 0000000000000000b

8.6.7 CFG Register (Address = 6h) [reset = 0600h]

The CFG register is shown in Figure 8-32 and described in Table 8-20.

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Figure 8-32 CFG Register
15141312111098
RESERVEDGC_DLY[3:0]GC_EN
R/W-000bR/W-0011bR/W-0b
76543210
CD_ALLCHCD_NUM[2:0]CD_LEN[2:0]CD_EN
R/W-0bR/W-000bR/W-000bR/W-0b
Table 8-20 CFG Register Field Descriptions
BitFieldTypeResetDescription
15:13RESERVEDR/W000b

Reserved

Always write 000b

12:9GC_DLY[3:0]R/W0011b

Global-chop delay selection

Delay in modulator clock periods before measurement begins

0000b = 2

0001b = 4

0010b = 8

0011b = 16 (default)

0100b = 32

0101b = 64

0110b = 128

0111b = 256

1000b = 512

1001b = 1024

1010b = 2048

1011b = 4096

1100b = 8192

1101b = 16384

1110b = 32768

1111b = 65536

8GC_ENR/W0b

Global-chop enable

0b = Disabled (default)

1b = Enabled

7CD_ALLCHR/W0b

Current-detect channel selection

Channels required to trigger current-detect

0b = Any channel (default)

1b = All channels

6:4CD_NUM[2:0]R/W000b

Number of current-detect exceeded thresholds selection

Number of current-detect exceeded thresholds to trigger a detection

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

3:1CD_LEN[2:0]R/W000b

Current-detect measurement length selection

Current-detect measurement length in conversion periods

000b = 128 (default)

001b = 256

010b = 512

011b = 768

100b = 1280

101b = 1792

110b = 2560

111b = 3584

0CD_ENR/W0b

Current-detect mode enable

0b = Disabled (default)

1b = Enabled

8.6.8 THRSHLD_MSB Register (Address = 7h) [reset = 0000h]

The THRSHLD_MSB register is shown in Figure 8-33 and described in Table 8-21.

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Figure 8-33 THRSHLD_MSB Register
15141312111098
CD_TH_MSB[15:8]
R/W-00000000b
76543210
CD_TH_MSB[7:0]
R/W-00000000b
Table 8-21 THRSHLD_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0CD_TH_MSB[15:0]R/W00000000
00000000b

Current-detect mode threshold MSB

8.6.9 THRSHLD_LSB Register (Address = 8h) [reset = 0000h]

The THRSHLD_LSB register is shown in Figure 8-34 and described in Table 8-22.

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Figure 8-34 THRSHLD_LSB Register
15141312111098
CD_TH_LSB[7:0]
R/W-00000000b
76543210
RESERVEDDCBLOCK
R-0000bR/W-0000b
Table 8-22 THRSHLD_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8CD_TH_LSB[7:0]R/W00000000b

Current-detect mode threshold LSB

7:4RESERVEDR0000b

Reserved

Always write 0000b

3:0DCBLOCK[3:0]R/W0000b

DC block filter setting, see Table 8-4 for details.

Value of coefficient a

0000b = DC block filter disabled

0001b = 1/4

0010b = 1/8

0011b = 1/16

0100b = 1/32

0101b = 1/64

0110b = 1/128

0111b = 1/256

1000b = 1/512

1001b = 1/1024

1010b = 1/2048

1011b = 1/4096

1100b = 1/8192

1101b = 1/16384

1110b = 1/32768

1111b = 1/65536

8.6.10 CH0_CFG Register (Address = 9h) [reset = 0000h]

The CH0_CFG register is shown in Figure 8-35 and described in Table 8-23.

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Figure 8-35 CH0_CFG Register
15141312111098
PHASE0[9:2]
R/W-0000000000b
76543210
PHASE0[1:0]RESERVEDDCBLK0_DIS0MUX0[1:0]
R/W-0000000000bR-000bR/W-0bR/W-00b
Table 8-23 CH0_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:6PHASE0[9:0]R/W0000000000b

Channel 0 phase delay

Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.

5:3RESERVEDR000b

Reserved

Always write 000b

2DCBLK0_DIS0R/W0b

DC block filter for channel 0 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0MUX0[1:0]R/W00b

Channel 0 input selection

00b = AIN0P and AIN0N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

8.6.11 CH0_OCAL_MSB Register (Address = Ah) [reset = 0000h]

The CH0_OCAL_MSB register is shown in Figure 8-36 and described in Table 8-24.

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Figure 8-36 CH0_OCAL_MSB Register
15141312111098
OCAL0_MSB[15:8]
R/W-00000000b
76543210
OCAL0_MSB[7:0]
R/W-00000000b
Table 8-24 CH0_OCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0OCAL0_MSB[15:0]R/W00000000
00000000b

Channel 0 offset calibration register bits [23:8]

8.6.12 CH0_OCAL_LSB Register (Address = Bh) [reset = 0000h]

The CH0_OCAL_LSB register is shown in Figure 8-37 and described in Table 8-25.

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Figure 8-37 CH0_OCAL_LSB Register
15141312111098
OCAL0_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-25 CH0_OCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8OCAL0_LSB[7:0]R/W00000000b

Channel 0 offset calibration register bits [7:0]

7:0RESERVEDR00000000b

Reserved

Always reads 00000000b

8.6.13 CH0_GCAL_MSB Register (Address = Ch) [reset = 8000h]

The CH0_GCAL_MSB register is shown in Figure 8-38 and described in Table 8-26.

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Figure 8-38 CH0_GCAL_MSB Register
15141312111098
GCAL0_MSB[15:8]
R/W-10000000b
76543210
GCAL0_MSB[7:0]
R/W-00000000b
Table 8-26 CH0_GCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0GCAL0_MSB[15:0]R/W1000000000000000b

Channel 0 gain calibration register bits [23:8]

8.6.14 CH0_GCAL_LSB Register (Address = Dh) [reset = 0000h]

The CH0_GCAL_LSB register is shown in Figure 8-39 and described in Table 8-27.

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Figure 8-39 CH0_GCAL_LSB Register
15141312111098
GCAL0_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-27 CH0_GCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8GCAL0_LSB[7:0]R/W00000000b

Channel 0 gain calibration register bits [7:0]

7:0RESERVEDR00000000b

Reserved

Always reads 00000000b

8.6.15 CH1_CFG Register (Address = Eh) [reset = 0000h]

The CH1_CFG register is shown in Figure 8-40 and described in Table 8-28.

Return to the Summary Table.

Figure 8-40 CH1_CFG Register
15141312111098
PHASE1[9:2]
R/W-0000000000b
76543210
PHASE1[1:0]RESERVEDDCBLK1_DIS0MUX1[1:0]
R/W-0000000000bR-000bR/W-0bR/W-00b
Table 8-28 CH1_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:6PHASE1[9:0]R/W0000000000b

Channel 1 phase delay

Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.

5:3RESERVEDR000b

Reserved

Always reads 000b

2DCBLK1_DIS0R/W0b

DC block filter for channel 1 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0MUX1[1:0]R/W00b

Channel 1 input selection

00b = AIN1P and AIN1N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

8.6.16 CH1_OCAL_MSB Register (Address = Fh) [reset = 0000h]

The CH1_OCAL_MSB register is shown in Figure 8-41 and described in Table 8-29.

Return to the Summary Table.

Figure 8-41 CH1_OCAL_MSB Register
15141312111098
OCAL1_MSB[15:8]
R/W-00000000b
76543210
OCAL1_MSB[7:0]
R/W-00000000b
Table 8-29 CH1_OCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0OCAL1_MSB[15:0]R/W00000000
00000000b

Channel 1 offset calibration register bits [23:8]

8.6.17 CH1_OCAL_LSB Register (Address = 10h) [reset = 0000h]

The CH1_OCAL_LSB register is shown in Figure 8-42 and described in Table 8-30.

Return to the Summary Table.

Figure 8-42 CH1_OCAL_LSB Register
15141312111098
OCAL1_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-30 CH1_OCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8OCAL1_LSB[7:0]R/W00000000b

Channel 1 offset calibration register bits [7:0]

7:0RESERVEDR00000000b

Reserved

Always reads 00000000b

8.6.18 CH1_GCAL_MSB Register (Address = 11h) [reset = 8000h]

The CH1_GCAL_MSB register is shown in Figure 8-43 and described in Table 8-31.

Return to the Summary Table.

Figure 8-43 CH1_GCAL_MSB Register
15141312111098
GCAL1_MSB[15:8]
R/W-10000000b
76543210
GCAL1_MSB[7:0]
R/W-00000000b
Table 8-31 CH1_GCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0GCAL1_MSB[15:0]R/W1000000000000000b

Channel 1 gain calibration register bits [23:8]

8.6.19 CH1_GCAL_LSB Register (Address = 12h) [reset = 0000h]

The CH1_GCAL_LSB register is shown in Figure 8-44 and described in Table 8-32.

Return to the Summary Table.

Figure 8-44 CH1_GCAL_LSB Register
15141312111098
GCAL1_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-32 CH1_GCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8GCAL1_LSB[7:0]R/W00000000b

Channel 1 gain calibration register bits [7:0]

7:0RESERVEDR00000000b

Reserved

Always reads 00000000b

8.6.20 CH2_CFG Register (Address = 13h) [reset = 0000h]

The CH2_CFG register is shown in Figure 8-45 and described in Table 8-33.

Return to the Summary Table.

Figure 8-45 CH2_CFG Register
15141312111098
PHASE2[9:2]
R/W-0000000000b
76543210
PHASE2[2:0]RESERVEDDCBLK2_DIS0MUX2[1:0]
R/W-0000000000bR-000bR/W-0bR/W-00b
Table 8-33 CH2_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:6PHASE2[9:0]R/W0000000000b

Channel 2 phase delay

Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.

5:3RESERVEDR000b

Reserved

Always reads 000b

2DCBLK2_DIS0R/W0b

DC block filter for channel 2 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0MUX2[1:0]R/W00b

Channel 2 input selection

00b = AIN2P and AIN2N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

8.6.21 CH2_OCAL_MSB Register (Address = 14h) [reset = 0000h]

The CH2_OCAL_MSB register is shown in Figure 8-46 and described in Table 8-34.

Return to the Summary Table.

Figure 8-46 CH2_OCAL_MSB Register
15141312111098
OCAL2_MSB[15:8]
R/W-00000000b
76543210
OCAL2_MSB[7:0]
R/W-00000000b
Table 8-34 CH2_OCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0OCAL2_MSB[15:0]R/W00000000
00000000b

Channel 2 offset calibration register bits [23:8]

8.6.22 CH2_OCAL_LSB Register (Address = 15h) [reset = 0000h]

The CH2_OCAL_LSB register is shown in Figure 8-47 and described in Table 8-35.

Return to the Summary Table.

Figure 8-47 CH2_OCAL_LSB Register
15141312111098
OCAL2_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-35 CH2_OCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8OCAL2_LSB[7:0]R/W00000000b

Channel 2 offset calibration register bits [7:0]

7:0RESERVEDR00000000b

Reserved

Always reads 00000000b

8.6.23 CH2_GCAL_MSB Register (Address = 16h) [reset = 8000h]

The CH2_GCAL_MSB register is shown in Figure 8-48 and described in Table 8-36.

Return to the Summary Table.

Figure 8-48 CH2_GCAL_MSB Register
15141312111098
GCAL2_MSB[15:8]
R/W-10000000b
76543210
GCAL2_MSB[7:0]
R/W-00000000b
Table 8-36 CH2_GCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0GCAL2_MSB[15:0]R/W1000000000000000b

Channel 2 gain calibration register bits [23:8]

8.6.24 CH2_GCAL_LSB Register (Address = 17h) [reset = 0000h]

The CH2_GCAL_LSB register is shown in Figure 8-49 and described in Table 8-37.

Return to the Summary Table.

Figure 8-49 CH2_GCAL_LSB Register
15141312111098
GCAL2_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-37 CH2_GCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8GCAL2_LSB[7:0]R/W00000000b

Channel 2 gain calibration register bits [7:0]

7:0RESERVEDR00000000b

Reserved

Always reads 00000000b

8.6.25 CH3_CFG Register (Address = 18h) [reset = 0000h]

The CH3_CFG register is shown in Figure 8-50 and described in Table 8-38.

Return to the Summary Table.

Figure 8-50 CH3_CFG Register
15141312111098
PHASE3[9:2]
R/W-0000000000b
76543210
PHASE3[1:0]RESERVEDDCBLK3_DIS0MUX3[1:0]
R/W-0000000000bR-000bR/W-0bR/W-00b
Table 8-38 CH3_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:6PHASE3[9:0]R/W0000000000b

Channel 3 phase delay

Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.

5:3RESERVEDR000b

Reserved

Always reads 000b

2DCBLK3_DIS0R/W0b

DC block filter for channel 3 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0MUX3[1:0]R/W00b

Channel 3 input selection

00b = AIN3P and AIN3N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

8.6.26 CH3_OCAL_MSB Register (Address = 19h) [reset = 0000h]

The CH3_OCAL_MSB register is shown in Figure 8-51 and described in Table 8-39.

Return to the Summary Table.

Figure 8-51 CH3_OCAL_MSB Register
15141312111098
OCAL3_MSB[15:8]
R/W-00000000b
76543210
OCAL3_MSB[7:0]
R/W-00000000b
Table 8-39 CH3_OCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0OCAL3_MSB[15:0]R/W00000000
00000000b

Channel 3 offset calibration register bits [23:8]

8.6.27 CH3_OCAL_LSB Register (Address = 1Ah) [reset = 0000h]

The CH3_OCAL_LSB register is shown in Figure 8-52 and described in Table 8-40.

Return to the Summary Table.

Figure 8-52 CH3_OCAL_LSB Register
15141312111098
OCAL3_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-40 CH3_OCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8OCAL3_LSB[7:0]R/W00000000b

Channel 3 offset calibration register bits [7:0]

7:0RESERVEDR00000000b

Reserved

Always reads 00000000b

8.6.28 CH3_GCAL_MSB Register (Address = 1Bh) [reset = 8000h]

The CH3_GCAL_MSB register is shown in Figure 8-53 and described in Table 8-41.

Return to the Summary Table.

Figure 8-53 CH3_GCAL_MSB Register
15141312111098
GCAL3_MSB[15:8]
R/W-10000000b
76543210
GCAL3_MSB[7:0]
R/W-00000000b
Table 8-41 CH3_GCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0GCAL3_MSB[15:0]R/W1000000000000000b

Channel 3 gain calibration register bits [23:8]

8.6.29 CH3_GCAL_LSB Register (Address = 1Ch) [reset = 0000h]

The CH3_GCAL_LSB register is shown in Figure 8-54 and described in Table 8-42.

Return to the Summary Table.

Figure 8-54 CH3_GCAL_LSB Register
15141312111098
GCAL3_LSB[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-42 CH3_GCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8GCAL3_LSB[7:0]R/W00000000b

Channel 3 gain calibration register bits [7:0]

7:0RESERVEDR00000000b

Reserved

Always reads 00000000b

8.6.30 REGMAP_CRC Register (Address = 3Eh) [reset = 0000h]

The REGMAP_CRC register is shown in Figure 8-55 and described in Table 8-43.

Return to the Summary Table.

Figure 8-55 REGMAP_CRC Register
15141312111098
REG_CRC[15:8]
R-0000000000000000b
76543210
REG_CRC[7:0]
R-0000000000000000b
Table 8-43 REGMAP_CRC Register Field Descriptions
BitFieldTypeResetDescription
15:0REG_CRC[15:0]R00000000
00000000b

Register map CRC

8.6.31 RESERVED Register (Address = 3Fh) [reset = 0000h]

The RESERVED register is shown in Figure 8-56 and described in Table 8-44.

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Figure 8-56 RESERVED Register
15141312111098
RESERVED
R/W-00000000b
76543210
RESERVED
R/W-00000000b
Table 8-44 RESERVED Register Field Descriptions
BitFieldTypeResetDescription
15:0RESERVEDR/W00000000
00000000b

Reserved,

Always write 0000000000000000b