JAJSML5A March 2022 – August 2022 ADS131M04-Q1
PRODUCTION DATA
Table 9-1 lists common issues faced when designing with the ADS131M04-Q1 and the corresponding solutions. This list is not comprehensive.
ISSUE | POSSIBLE ROOT CAUSE | POSSIBLE SOLUTION |
---|---|---|
The DRDY pin is toggling at half the expected frequency. | ADC conversion data are not being read. The two-deep ADC data FIFO overflows and triggers DRDY one time every two ADC data periods. | Read data after each DRDY falling edge after following the recommendations given in the Section 8.5.1.9.1 section. |
The F_RESYNC bit is set in the STATUS word even though this bit was already cleared. | The SYNC/RESET pin is being toggled asynchronously to CLKIN. | The SYNC/RESET pin functions as a constant synchronization check, rather than a convert start pin. See the Section 8.5.2 section for more details on the intended usage of the SYNC/RESET pin. |
The same ADC conversion data are output twice before changing. | The entire frame is not being sent to the ADC. The ADC does not recognize data as being read. | Read all data words in the output data frame, including those for channels that are disabled. |