JAJSML5A
March 2022 – August 2022
ADS131M04-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Timing Diagrams
6.9
Typical Characteristics
7
Parameter Measurement Information
7.1
Noise Measurements
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Input ESD Protection Circuitry
8.3.2
Input Multiplexer
8.3.3
Programmable Gain Amplifier (PGA)
8.3.4
Voltage Reference
8.3.5
Clocking and Power Modes
8.3.6
ΔΣ Modulator
8.3.7
Digital Filter
8.3.7.1
Digital Filter Implementation
8.3.7.1.1
Fast-Settling Filter
8.3.7.1.2
SINC3 and SINC3 + SINC1 Filter
8.3.7.2
Digital Filter Characteristic
8.3.8
DC Block Filter
8.3.9
Internal Test Signals
8.3.10
Channel Phase Calibration
8.3.11
Calibration Registers
8.3.12
Communication Cyclic Redundancy Check (CRC)
8.3.13
Register Map CRC
8.4
Device Functional Modes
8.4.1
Power-Up and Reset
8.4.1.1
Power-On Reset
8.4.1.2
SYNC/RESET Pin
8.4.1.3
RESET Command
8.4.2
Fast Start-Up Behavior
8.4.3
Conversion Modes
8.4.3.1
Continuous-Conversion Mode
8.4.3.2
Global-Chop Mode
8.4.4
Power Modes
8.4.5
Standby Mode
8.4.6
Current-Detect Mode
8.5
Programming
8.5.1
Interface
8.5.1.1
Chip Select (CS)
8.5.1.2
Serial Data Clock (SCLK)
8.5.1.3
Serial Data Input (DIN)
8.5.1.4
Serial Data Output (DOUT)
8.5.1.5
Data Ready (DRDY)
8.5.1.6
Conversion Synchronization or System Reset (SYNC/RESET)
8.5.1.7
SPI Communication Frames
8.5.1.8
SPI Communication Words
8.5.1.9
ADC Conversion Data
8.5.1.9.1
Collecting Data for the First Time or After a Pause in Data Collection
8.5.1.10
Commands
8.5.1.10.1
NULL (0000 0000 0000 0000)
8.5.1.10.2
RESET (0000 0000 0001 0001)
8.5.1.10.3
STANDBY (0000 0000 0010 0010)
8.5.1.10.4
WAKEUP (0000 0000 0011 0011)
8.5.1.10.5
LOCK (0000 0101 0101 0101)
8.5.1.10.6
UNLOCK (0000 0110 0101 0101)
8.5.1.10.7
RREG (101a aaaa annn nnnn)
8.5.1.10.7.1
Reading a Single Register
8.5.1.10.7.2
Reading Multiple Registers
8.5.1.10.8
WREG (011a aaaa annn nnnn)
8.5.1.11
Short SPI Frames
8.5.2
Synchronization
8.6
ADS131M04-Q1 Registers
9
Application and Implementation
9.1
Application Information
9.1.1
Unused Inputs and Outputs
9.1.2
Antialiasing
9.1.3
Minimum Interface Connections
9.1.4
Multiple Device Configuration
9.1.5
Troubleshooting
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Current Shunt Measurement
9.2.2.2
Battery Pack Voltage Measurement
9.2.3
Application Curve
9.3
Power Supply Recommendations
9.3.1
CAP Pin Behavior
9.3.2
Power-Supply Sequencing
9.3.3
Power-Supply Decoupling
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
サポート・リソース
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PW|20
MPDS362A
サーマルパッド・メカニカル・データ
発注情報
jajsml5a_oa
jajsml5a_pm
8
Detailed Description