JAJSML5A March   2022  – August 2022 ADS131M04-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. 8.3.7.1 Digital Filter Implementation
          1. 8.3.7.1.1 Fast-Settling Filter
          2. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.7.2 Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0101 0101)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 ADS131M04-Q1 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 CAP Pin Behavior
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Typical Characteristics

at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global-chop mode disabled (unless otherwise noted)

GUID-20210520-CA0I-XPC2-Q3D9-NKHFDZRZSLCK-low.png
Gains of 8, 16, 32, 64, and 128 only
Figure 6-4 Input Bias Current vs Gain
 
Figure 6-6 Start-Up Time Histogram
GUID-2599CE17-4892-42EB-966F-E1DC7A318464-low.gif
 
Figure 6-8 Input Offset Voltage vs Temperature
18 units, all channels
Figure 6-10 Gain Error vs Time
 
Figure 6-12 DC CMRR vs Temperature
GUID-9D11DB31-50ED-4003-9368-F3043EFEF000-low.gif
 
Figure 6-14 AVDD CMRR vs Frequency
GUID-39719DCD-FDF1-453E-BF57-635835D28BF3-low.gif
 
Figure 6-16 DC AVDD PSRR vs Temperature
Gain = 1, inputs shorted
Figure 6-18 Single Device Noise Histogram at 4 kSPS
GUID-20210116-CA0I-FRVK-W8C1-8GJCMRZDBRCR-low.gif
 
Figure 6-20 Noise vs Temperature
GUID-8973D4AD-5B09-4BD4-80D4-BD1784E160BE-low.gif
 
Figure 6-22 Dynamic Range vs Gain
GUID-20210116-CA0I-WLCK-ND1K-4L98KXC4JJV7-low.gif
 
Figure 6-24 Crosstalk vs Channel
GUID-A6FA0DDF-D73A-40B3-891D-F5BA35609297-low.gif
 
Figure 6-26 THD vs AVDD Voltage
GUID-94F77BD5-BBE8-4EF3-BC1A-9F29D3D46FA8-low.gif
 
Figure 6-28 AVDD Current vs CLKIN Frequency
 
Figure 6-5 Input Impedance vs Gain
GUID-4A536DFE-A1CE-4246-BEC8-88FAB8B8C823-low.gif
30 units, channel 1
Figure 6-7 Input Offset Voltage vs Gain
Includes internal reference error
Figure 6-9 Gain Error vs Temperature
18 units, all channels
Figure 6-11 Gain Error vs Time Across Humidity
 
Figure 6-13 DC CMRR vs AVDD Voltage
GUID-079554B6-704F-4F03-983B-607EC62BF7CF-low.gif
 
Figure 6-15 AC CMRR vs AVDD Voltage
GUID-F07078DE-7828-43B5-939D-059B5E02F122-low.gif
 
Figure 6-17 DC DVDD PSRR vs Temperature
Gain = 1, inputs shorted
Figure 6-19 Single Device Noise Histogram at 32 kSPS
GUID-F0CB7944-D0DC-4430-947C-8116B1728372-low.gif
 
Figure 6-21 Dynamic Range at 4 kSPS vs Gain
GUID-198700ED-7612-4093-B086-DE27C2D9A80A-low.gif
 
Figure 6-23 Dynamic Range vs Gain
GUID-14798301-3699-4234-A268-06520EB368B3-low.gif
 
Figure 6-25 THD vs Gain
GUID-A1475515-4BF5-4AC9-9D42-8ECA7BA63177-low.gif
 
Figure 6-27 AVDD Current vs Gain
GUID-9DAC809A-7C6A-40DC-B100-F90B15731ED8-low.gif
 
Figure 6-29 DVDD Current vs CLKIN Frequency