JAJSML5A March   2022  – August 2022 ADS131M04-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. 8.3.7.1 Digital Filter Implementation
          1. 8.3.7.1.1 Fast-Settling Filter
          2. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.7.2 Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0101 0101)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 ADS131M04-Q1 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 CAP Pin Behavior
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.2 Battery Pack Voltage Measurement

The 800-V battery-pack voltage is divided down to the voltage range of the ADS131M04-Q1 using a high-voltage resistor divider (RH1, RH2, RH3, and RL). Gain = 1 is used for channel 0 in this case to allow differential voltage measurements of VIN0 = VAIN0P – VAIN0N = ±1.2 V. The battery-pack voltage measurement is a unipolar, single-ended measurement. Thus, only the voltage range from 0 V to 1.2 V of the ADS131M04-Q1 is used. Equation 11 calculates the resistor divider ratio.

Equation 11. VIN / VBAT_MAX = 1.2 V / 800 V = RL / (RL + RH1 + RH2 + RH3)

The leakage current drawn by the resistor divider must be less than 100 μA in this example to avoid unnecessarily draining the battery. The resistance of the divider must therefore be larger than RTOTAL ≥
VBAT_MAX / ILEAKAGE = 800 V / 100 μA = 8 MΩ. The resistor values are chosen as RH1 = RH2 = RH3 = 2.8 MΩ and RL = 12.4 kΩ. Thus, the maximum voltage across RL is 1.18 V at VBAT_MAX = 800 V, leaving some headroom to the maximum input voltage of 1.2 V of the ADS131M04-Q1.

The maximum resistance of a single resistor that can be used in an automotive circuit design is often limited to a certain value. Also, the maximum voltage a single resistor can withstand is limited. These reasons are why the high-side resistor of the divider is split into multiple resistors (RH1, RH2, and RH3). Another reason is that in case a single resistor has a short-circuit fault, the remaining resistors still limit the current into the ADS131M04-Q1 analog input pin (AIN0P) to safe levels.