JAJSML5A March   2022  – August 2022 ADS131M04-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. 8.3.7.1 Digital Filter Implementation
          1. 8.3.7.1.1 Fast-Settling Filter
          2. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.7.2 Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0101 0101)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 ADS131M04-Q1 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 CAP Pin Behavior
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.2 Fast Start-Up Behavior

The ADS131M04-Q1 begins generating conversion data shortly after startup as soon as a valid CLKIN signal is provided to the ΔΣ modulators. The fast start-up feature is useful for applications such as circuit breakers powered from the mains that require a fast determination of the input voltage soon after power is applied to the device. Fast start up is accomplished via two mechanisms. First, the device internal power-supply circuitry is designed specifically to enable fast start up. Second, the digital decimation filter dynamically switches from a fast-settling filter to a sinc3 filter when the sinc3 filter has had time to settle.

After the supplies are ramped to 90% of their final values, the device requires tPOR for the internal circuitry to settle. The end of tPOR is indicated by a transition of DRDY from low to high. The transition of DRDY from low to high also indicates the SPI interface is ready to accept commands.

The ΔΣ modulators of the ADS131M04-Q1 require CLKIN to toggle after tPOR to begin working. The modulators begin sampling the input signal after an initial wait time delay of (256 + 44) × tMOD when CLKIN begins toggling. Therefore, provide a valid clock signal on CLKIN as soon as possible after the supply ramp to achieve the fastest possible startup time.

The data generated by the ΔΣ modulators are fed to the digital filter blocks. The data are provided to both the fast-settling filter and the sinc3 filter paths. The fast-settling filter requires only one data rate period to provide settled data. Meanwhile, the sinc3 filter requires three data rate periods to settle. The fast-settling filter generates the output data for the two interim ADC output samples indicated by DRDY transitioning from high to low while the sinc3 filter is settling. The device disables the fast-settling filter and provides conversion data from the sinc3 filter path for the third and following samples. Figure 8-14 shows the behavior of the fast start-up feature when using an external clock that is provided to the device right after the supplies have ramped. Table 8-8 shows the values for the various start-up and settling times relevant to the device start up.

GUID-20201021-CA0I-CSHD-NFSN-PQFZVT5D3H7N-low.gif Figure 8-14 Fast Startup Behavior and Settling Times
Table 8-8 Fast Startup Settling Times for Default OSR = 1024
PARAMETER VALUE (DETAILS)
(tMOD) 		VALUE
(tMOD)		 VALUE AT
fCLKIN = 8.192 MHz (ms)
tDATA = 1/fDATA 1024 1024 0.250
tSETTLE1 256 + 44 + 1024 1324 0.323
tSETTLE3 256 + 44 + 3 x 1024 3372 0.823

The fast-settling filter provides conversion data that are significantly noisier than the data that comes from the sinc3 filter path, but allows the device to provide settled conversion data during the longer settling time of the more accurate sinc3 digital filter. If the level of precision provided by the fast-settling filter is insufficient even for the first samples immediately following start up, ignore the first two instances of DRDY toggling from high to low and begin collecting data on the third instance.

The start-up process following a RESET command or a pin reset using the SYNC/RESET pin is similar to what occurs after power up. However there is no tPOR in the case of a command or pin reset because the supplies are already ramped. After reset, the device waits for the initial wait time delay of (256 + 44) × tMOD before providing modulator samples to the two digital filters. The fast-settling filter is enabled for the first two output samples.