JAJSML5A March   2022  – August 2022 ADS131M04-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. 8.3.7.1 Digital Filter Implementation
          1. 8.3.7.1.1 Fast-Settling Filter
          2. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.7.2 Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0101 0101)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 ADS131M04-Q1 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 CAP Pin Behavior
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, all channels enabled, global-chop mode disabled and gain = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
IB Input bias current Gain = 1, 2, or 4, VINP = VINN = 0 V,
IB = (IBP + IBN) / 2		 0.6 µA
Input bias current
Gain = 8, 16, 32, 64 or 128, VINP = VINN =
0 V,  IB = (IBP + IBN) / 2		 0.2
Zin Differential input impedance Gain = 1, 2, or 4 300 kΩ
Gain = 8, 16, 32, 64, or 128 ±1 (1) µA/V
ADC CHARACTERISTICS
Resolution 24 Bits
Gain settings 1, 2, 4, 8, 16, 32, 64, 128
fDATA Data rate High-resolution mode, fCLKIN = 8.192 MHz 250 64k SPS
Low-power mode, fCLKIN = 4.096 MHz 125 32k
Very-low-power mode, fCLKIN = 2.048 MHz 62.5 16k
Startup time Measured from supplies at 90% to first DRDY falling edge 0.5 ms
ADC PERFORMANCE
INL Integral nonlinearity (best fit) 6 ppm of FSR
Offset error (input referred) ±175 µV
Global-chop mode, channel 0 ±35
Global-chop mode, channels 1-3 ±15
Offset drift 300 nV/°C
Global-chop mode 200
Offset error time drift 1000 hours at 85°C 4 μV
Gain error ±0.1%
Gain drift 1 ppm/°C
Including internal reference 8.5
Gain error time drift 1000 hours at 85°C 400 ppm
CMRR Common-mode rejection ratio At dc 100 dB
fCM = 50 Hz or 60 Hz 94
PSRR Power-supply rejection ratio AVDD at dc 75 dB
DVDD at dc 88
AVDD supply, fPS = 50 Hz or 60 Hz 78
DVDD supply, fPS = 50 Hz or 60 Hz 85
Input-referred noise 5.35 µVRMS
During fast-startup 1.5 mVRMS
Dynamic range Gain = 1 99 102 dB
Gain = 64 80
All other gain settings See  Table 7-1 
Crosstalk fIN = 50 Hz or 60 Hz –120 dB
SNR Signal-to-noise ratio fIN = 50 Hz or 60 Hz, gain = 1,
VIN = –0.5 dBFS, normalized		 100 dB
fIN = 50 Hz or 60 Hz, gain = 64,
VIN = –0.5 dBFS, normalized		 79
THD Total harmonic distortion fIN = 50 Hz or 60 Hz (up to 50 harmonics),
VIN = –0.5 dBFS		 –100 dB
SFDR Spurious-free dynamic range fIN = 50 Hz or 60 Hz (up to 50 harmonics),
VIN = –0.5 dBFS		 105 dB
INTERNAL VOLTAGE REFERENCE
VREF Internal reference voltage 1.2 V
Accuracy TA = 25°C ±0.1%
Temperature drift 7.5 20 ppm/°C
DIGITAL INPUTS/OUTPUTS
VIL Logic input level, low DGND 0.2 DVDD V
VIH Logic input level, high 0.8 DVDD DVDD V
VOL Logic output level, low IOL = –1 mA 0.2 DVDD V
VOH Logic output level, high IOH = 1 mA 0.8 DVDD V
IIN Input current DGND < VDigital Input < DVDD –1 1 µA
POWER SUPPLY
IAVDD Analog supply current High-resolution mode 3.5 4.0 mA
Low-power mode 2.0 2.2
Very-low-power mode 1.0 1.2
Current-detect mode 0.9 mA
Standby mode 0.3 µA
IDVDD Digital supply current(2) High-resolution mode 0.4 0.5 mA
Low-power mode 0.2 0.3
Very-low-power mode 0.1 0.2
Current-detect mode 0.065 mA
Standby mode 1 µA
PD Power dissipation High-resolution mode 12 mW
Low-power mode 6.6
Very-low-power mode 3.3
Current-detect mode 2.9
Standby mode 3.9 µW
(1) Specified in µA/V because current can flow either into or out of the input pin.
(2) Currents measured with SPI idle.