JAJSML5A March 2022 – August 2022 ADS131M04-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1.65 V ≤ DVDD ≤ 2.0 V | ||||||
tp(CSDO) | Propagation delay time, CS falling edge to DOUT driven | 50 | ns | |||
tp(SCDO) | Progapation delay time, SCLK rising edge to valid new DOUT | 32 | ns | |||
tp(CSDOZ) | Propagation delay time, CS rising edge to DOUT high impedance | 75 | ns | |||
tw(DRH) | Pulse duration, DRDY high | 4 | tCLKIN | |||
tw(DRL) | Pulse duration, DRDY low | 4 | tCLKIN | |||
SPI timeout | 32768 | tCLKIN | ||||
tPOR | Power-on-reset time | Measured from supplies at 90% to first DRDY rising edge | 250 | µs | ||
tREGACQ | Register default acquisition time | 5 | µs | |||
2.7 V ≤ DVDD ≤ 3.6 V | ||||||
tp(CSDO) | Propagation delay time, CS falling edge to DOUT driven | 50 | ns | |||
tp(SCDO) | Progapation delay time, SCLK rising edge to valid new DOUT | 20 | ns | |||
tp(CSDOZ) | Propagation delay time, CS rising edge to DOUT high impedance | 75 | ns | |||
tw(DRH) | Pulse duration, DRDY high | 4 | tCLKIN | |||
tw(DRL) | Pulse duration, DRDY low | 4 | tCLKIN | |||
SPI timeout | 32768 | tCLKIN | ||||
tPOR | Power-on-reset time | Measured from supplies at 90% to first DRDY rising edge | 250 | µs | ||
tREGACQ | Register default acquisition time | 5 | µs |