JAJSI11 データシート

Table 8-12 lists the ADS131M08 registers. All register offset addresses not listed in Table 8-12 should be considered as reserved locations and the register contents should not be modified.

Table 8-12 Register Map

ADDRESS	REGISTER	RESET VALUE	BIT 15	BIT 14	BIT 13	BIT 12	BIT 11	BIT 10	BIT 9	BIT 8
ADDRESS	REGISTER	RESET VALUE	BIT 7	BIT 6	BIT 5	BIT 4	BIT 3	BIT 2	BIT 1	BIT 0
DEVICE SETTINGS AND INDICATORS (Read-Only Registers)
00h	ID	28xxh	RESERVED				CHANCNT[3:0]
00h	ID	28xxh	RESERVED
01h	STATUS	0500h	LOCK	F_RESYNC	REG_MAP	CRC_ERR	CRC_TYPE	RESET	WLENGTH[1:0]
01h	STATUS	0500h	DRDY7	DRDY6	DRDY5	DRDY4	DRDY3	DRDY2	DRDY1	DRDY0
GLOBAL SETTINGS ACROSS CHANNELS
02h	MODE	0510h	RESERVED		REGCRC_EN	RX_CRC_EN	CRC_TYPE	RESET	WLENGTH[1:0]
02h	MODE	0510h	RESERVED			TIMEOUT	DRDY_SEL[1:0]		DRDY_HiZ	DRDY_FMT
03h	CLOCK	FF0Eh	CH7_EN	CH6_EN	CH5_EN	CH4_EN	CH3_EN	CH2_EN	CH1_EN	CH0_EN
03h	CLOCK	FF0Eh	RESERVED			OSR[2:0]			PWR[1:0]
04h	GAIN1	0000h	RESERVED	PGAGAIN3[2:0]			RESERVED	PGAGAIN2[2:0]
04h	GAIN1	0000h	RESERVED	PGAGAIN1[2:0]			RESERVED	PGAGAIN0[2:0]
05h	GAIN2	0000h	RESERVED	PGAGAIN7[2:0]			RESERVED	PGAGAIN6[2:0]
05h	GAIN2	0000h	RESERVED	PGAGAIN5[2:0]			RESERVED	PGAGAIN4[2:0]
06h	CFG	0600h	RESERVED			GC_DLY[3:0]				GC_EN
06h	CFG	0600h	CD_ALLCH	CD_NUM[2:0]			CD_LEN[2:0]			CD_EN
07h	THRSHLD_MSB	0000h	CD_TH_MSB[15:8]
07h	THRSHLD_MSB	0000h	CD_TH_MSB[7:0]
08h	THRSHLD_LSB	0000h	RESERVED				DCBLOCK[3:0]
CHANNEL-SPECIFIC SETTINGS
09h	CH0_CFG	0000h	PHASE0[9:2]
09h	CH0_CFG	0000h	PHASE0[1:0]		RESERVED			DCBLK0_DIS0	MUX0[1:0]
0Ah	CH0_OCAL_MSB	0000h	OCAL0_MSB[15:8]
0Ah	CH0_OCAL_MSB	0000h	OCAL0_MSB[7:0]
0Bh	CH0_OCAL_LSB	0000h	OCAL0_LSB[7:0]
0Bh	CH0_OCAL_LSB	0000h	RESERVED
0Ch	CH0_GCAL_MSB	8000h	GCAL0_MSB[15:8]
0Ch	CH0_GCAL_MSB	8000h	GCAL0_MSB[7:0]
0Dh	CH0_GCAL_LSB	0000h	GCAL0_LSB[7:0]
0Dh	CH0_GCAL_LSB	0000h	RESERVED
0Eh	CH1_CFG	0000h	PHASE1[9:2]
0Eh	CH1_CFG	0000h	PHASE1[1:0]		RESERVED			DCBLK1_DIS0	MUX1[1:0]
0Fh	CH1_OCAL_MSB	0000h	OCAL1_MSB[15:8]
0Fh	CH1_OCAL_MSB	0000h	OCAL1_MSB[7:0]
10h	CH1_OCAL_LSB	0000h	OCAL1_LSB[7:0]
10h	CH1_OCAL_LSB	0000h	RESERVED
11h	CH1_GCAL_MSB	8000h	GCAL1_MSB[15:8]
11h	CH1_GCAL_MSB	8000h	GCAL1_MSB[7:0]
12h	CH1_GCAL_LSB	0000h	GCAL1_LSB[7:0]
12h	CH1_GCAL_LSB	0000h	RESERVED
13h	CH2_CFG	0000h	PHASE2[9:2]
13h	CH2_CFG	0000h	PHASE2[1:0]		RESERVED			DCBLK2_DIS0	MUX2[1:0]
14h	CH2_OCAL_MSB	0000h	OCAL2_MSB[15:8]
14h	CH2_OCAL_MSB	0000h	OCAL2_MSB[7:0]
15h	CH2_OCAL_LSB	0000h	OCAL2_LSB[7:0]
15h	CH2_OCAL_LSB	0000h	RESERVED
16h	CH2_GCAL_MSB	8000h	GCAL2_MSB[15:8]
16h	CH2_GCAL_MSB	8000h	GCAL2_MSB[7:0]
17h	CH2_GCAL_LSB	0000h	GCAL2_LSB[7:0]
17h	CH2_GCAL_LSB	0000h	RESERVED
18h	CH3_CFG	0000h	PHASE3[9:2]
18h	CH3_CFG	0000h	PHASE3[1:0]		RESERVED			DCBLK3_DIS0	MUX3[1:0]
19h	CH3_OCAL_MSB	0000h	OCAL3_MSB[15:8]
19h	CH3_OCAL_MSB	0000h	OCAL3_MSB[7:0]
1Ah	CH3_OCAL_LSB	0000h	OCAL3_LSB[7:0]
1Ah	CH3_OCAL_LSB	0000h	RESERVED
1Bh	CH3_GCAL_MSB	8000h	GCAL3_MSB[15:8]
1Bh	CH3_GCAL_MSB	8000h	GCAL3_MSB[7:0]
1Ch	CH3_GCAL_LSB	0000h	GCAL3_LSB[7:0]
1Ch	CH3_GCAL_LSB	0000h	RESERVED
1Dh	CH4_CFG	0000h	PHASE4[9:2]
1Dh	CH4_CFG	0000h	PHASE4[1:0]		RESERVED			DCBLK4_DIS0	MUX4[1:0]
1Eh	CH4_OCAL_MSB	0000h	OCAL4_MSB[15:8]
1Eh	CH4_OCAL_MSB	0000h	OCAL4_MSB[7:0]
1Fh	CH4_OCAL_LSB	0000h	OCAL4_LSB[7:0]
1Fh	CH4_OCAL_LSB	0000h	RESERVED
20h	CH4_GCAL_MSB	8000h	GCAL4_MSB[15:8]
20h	CH4_GCAL_MSB	8000h	GCAL4_MSB[7:0]
21h	CH4_GCAL_LSB	0000h	GCAL4_LSB[7:0]
21h	CH4_GCAL_LSB	0000h	RESERVED
22h	CH5_CFG	0000h	PHASE5[9:2]
22h	CH5_CFG	0000h	PHASE5[1:0]		RESERVED			DCBLK5_DIS0	MUX5[1:0]
23h	CH5_OCAL_MSB	0000h	OCAL5_MSB[15:8]
23h	CH5_OCAL_MSB	0000h	OCAL5_MSB[7:0]
24h	CH5_OCAL_LSB	0000h	OCAL5_LSB[7:0]
24h	CH5_OCAL_LSB	0000h	RESERVED
25h	CH5_GCAL_MSB	8000h	GCAL5_MSB[15:8]
25h	CH5_GCAL_MSB	8000h	GCAL5_MSB[7:0]
26h	CH5_GCAL_LSB	0000h	GCAL5_LSB[7:0]
26h	CH5_GCAL_LSB	0000h	RESERVED
27h	CH6_CFG	0000h	PHASE6[9:2]
27h	CH6_CFG	0000h	PHASE6[1:0]		RESERVED			DCBLK6_DIS0	MUX6[1:0]
28h	CH6_OCAL_MSB	0000h	OCAL6_MSB[15:8]
28h	CH6_OCAL_MSB	0000h	OCAL6_MSB[7:0]
29h	CH6_OCAL_LSB	0000h	OCAL6_LSB[7:0]
29h	CH6_OCAL_LSB	0000h	RESERVED
2Ah	CH6_GCAL_MSB	8000h	GCAL6_MSB[15:8]
2Ah	CH6_GCAL_MSB	8000h	GCAL6_MSB[7:0]
2Bh	CH6_GCAL_LSB	0000h	GCAL6_LSB[7:0]
2Bh	CH6_GCAL_LSB	0000h	RESERVED
2Ch	CH7_CFG	0000h	PHASE7[9:2]
2Ch	CH7_CFG	0000h	PHASE7[1:0]		RESERVED			DCBLK7_DIS0	MUX7[1:0]
2Dh	CH7_OCAL_MSB	0000h	OCAL7_MSB[15:8]
2Dh	CH7_OCAL_MSB	0000h	OCAL7_MSB[7:0]
2Eh	CH7_OCAL_LSB	0000h	OCAL7_LSB[7:0]
2Eh	CH7_OCAL_LSB	0000h	RESERVED
2Fh	CH7_GCAL_MSB	8000h	GCAL7_MSB[15:8]
2Fh	CH7_GCAL_MSB	8000h	GCAL7_MSB[7:0]
30h	CH7_GCAL_LSB	0000h	GCAL7_LSB[7:0]
30h	CH7_GCAL_LSB	0000h	RESERVED
3Eh	REGMAP_CRC	0000h	REG_CRC[7:0]
3Fh	RESERVED	0000h	RESERVED
3Fh	RESERVED	0000h	RESERVED

Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for access types in this section.

Table 8-13 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.6.1 ID Register (Address = 00h) [reset = 28xxh]

The ID register is shown in Figure 8-26 and described in Table 8-14.

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Figure 8-26 ID Register

15	14	13	12	11	10	9	8
RESERVED				CHANCNT[3:0]
R-0010b				R-1000b

7	6	5	4	3	2	1	0
RESERVED
R-xxxxxxxxb

Table 8-14 ID Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R	0010b	Reserved always reads 0010b.
11:8	CHANCNT[3:0]	R	1000b	Channel count always reads 1000b.
7:0	RESERVED	R	xxxxxxxxb	Reserved Values are subject to change without notice

8.6.2 STATUS Register (Address = 01h) [reset = 0500h]

The STATUS register is shown in Figure 8-27 and described in Table 8-15.

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Figure 8-27 STATUS Register

15	14	13	12	11	10	9	8
LOCK	F_RESYNC	REG_MAP	CRC_ERR	CRC_TYPE	RESET	WLENGTH[1:0]
R-0b	R-0b	R-0b	R-0b	R-0b	R-1b	R-01b

7	6	5	4	3	2	1	0
DRDY7	DRDY6	DRDY5	DRDY4	DRDY3	DRDY2	DRDY1	DRDY0
R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b

Table 8-15 STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15	LOCK	R	0b	SPI interface lock indicator 0b = Unlocked (default) 1b = Locked
14	F_RESYNC	R	0b	ADC resynchronization indicator. Bit is set each time the ADC resynchronizes. 0b = No resynchronization (default) 1b = Resynchronization occurred
13	REG_MAP	R	0b	Register map CRC fault indicator 0b = No change in the register map CRC (default) 1b = Register map CRC changed
12	CRC_ERR	R	0b	SPI input CRC error indicator 0b = No CRC error (default) 1b = Input CRC error occured
11	CRC_TYPE	R	0b	CRC type 0b = 16 bit CCITT (default) 1b = 16 bit ANSI
10	RESET	R	1b	Reset status 0b = Not reset 1b = Reset occured (default)
9:8	WLENGTH[1:0]	R	01b	Data word length 00b = 16 bit 01b = 24 bits (default) 10b = 32 bits - zero padding 11b = 32 bits - sign extension for 24 bit ADC data
7	DRDY7	R	0b	Channel 7 ADC data available indicator 0b = No new data available 1b = New data are available
6	DRDY6	R	0b	Channel 6 ADC data available indicator 0b = No new data available 1b = New data are available
5	DRDY5	R	0b	Channel 5 ADC data available indicator 0b = No new data available 1b = New data are available
4	DRDY4	R	0b	Channel 4 ADC data available indicator 0b = No new data available 1b = New data are available
3	DRDY3	R	0b	Channel 3 ADC data available indicator 0b = No new data available 1b = New data are available
2	DRDY2	R	0b	Channel 2 ADC data available indicator 0b = No new data available 1b = New data are available
1	DRDY1	R	0b	Channel 1 ADC data available indicator 0b = No new data available 1b = New data are available
0	DRDY0	R	0b	Channel 0 ADC data available indicator 0b = No new data available 1b = New data are available

8.6.3 MODE Register (Address = 02h) [reset = 0510h]

The MODE register is shown in Figure 8-28 and described in Table 8-16.

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Figure 8-28 MODE Register

15	14	13	12	11	10	9	8
RESERVED		REG_CRC_EN	RX_CRC_EN	CRC_TYPE	RESET	WLENGTH[1:0]
R/W-00b		R/W-0b	R/W-0b	R/W-0b	R/W-1b	R/W-01b

7	6	5	4	3	2	1	0
RESERVED			TIMEOUT	DRDY_SEL[1:0]		DRDY_HiZ	DRDY_FMT
R/W-000b			R/W-1b	R/W-00b		R/W-0b	R/W-0b

Table 8-16 MODE Register Field Descriptions

Bit	Field	Type	Reset	Description
15:14	RESERVED	R/W	00b	Reserved always reads 00b
13	REG_CRC_EN	R/W	0b	Register Map CRC enable 0b = Disabled (default) 1b = Enabled
12	RX_CRC_EN	R/W	0b	SPI input CRC enable 0b = Disabled (default) 1b = Enabled
11	CRC_TYPE	R/W	0b	SPI and register map CRC type 0b = 16-bit CCITT (default) 1b = 16-bit ANSI
10	RESET	R/W	1b	Reset write 0b to clear this bit in the STATUS register 0b = No reset 1b = Reset happened (default by definition)
9:8	WLENGTH[1:0]	R/W	01b	Data word length selection 00b = 16 bits 01b = 24 bits (default) 10b = 32 bits: LSB zero padding 11b = 32 bits: MSB sign extension
7:5	RESERVED	R/W	000b	Reserved always write 000b
4	TIMEOUT	R/W	1b	SPI Timeout enable 0b = Disabled 1b = Enabled (default)
3:2	DRDY_SEL[1:0]	R/W	00b	DRDY pin signal source selection 00b = Most lagging enabled channel (default) 01b = Logic OR of all the enabled channels 10b = Most leading enabled channel 11b = Most leading enabled channel
1	DRDY_HiZ	R/W	0b	DRDY pin state when conversion data is not available 0b = Logic high (default) 1b = High impedance
0	DRDY_FMT	R/W	0b	DRDY signal format when conversion data is available 0b = Logic low (default) 1b = Low pulse with a fixed duration

8.6.4 CLOCK Register (Address = 03h) [reset = FF0Eh]

The CLOCK register is shown in Figure 8-29 and described in Table 8-17.

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Figure 8-29 CLOCK Register

15	14	13	12	11	10	9	8
CH7_EN	CH6_EN	CH5_EN	CH4_EN	CH3_EN	CH2_EN	CH1_EN	CH0_EN
R/W-1b	R/W-1b	R/W-1b	R/W-1b	R/W-1b	R/W-1b	R/W-1b	R/W-1b

7	6	5	4	3	2	1	0
XTAL_DIS	EXTREF_EN	RESERVED	OSR[2:0]			PWR
R/W-0b	R/W-0b	R/W-0b	R/W-011b			R/W-10b

Table 8-17 CLOCK Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CH7_EN	R/W	1b	Channel 7 ADC enable 0b = Disabled 1b = Enabled (default)
14	CH6_EN	R/W	1b	Channel 6 ADC enable 0b = Disabled 1b = Enabled (default)
13	CH5_EN	R/W	1b	Channel 5 ADC enable 0b = Disabled 1b = Enabled (default)
12	CH4_EN	R/W	1b	Channel 4 ADC enable 0b = Disabled 1b = Enabled (default)
11	CH3_EN	R/W	1b	Channel 3 ADC enable 0b = Disabled 1b = Enabled (default)
10	CH2_EN	R/W	1b	Channel 2 ADC enable 0b = Disabled 1b = Enabled (default)
9	CH1_EN	R/W	1b	Channel 1 ADC enable 0b = Disabled 1b = Enabled (default)
8	CH0_EN	R/W	1b	Channel 0 ADC enable 0b = Disabled 1b = Enabled (default)
7	XTAL_DIS	R/W	0b	Crystal oscillator disable 0b = Enabled (default) 1b = Disabled
6	EXTREF_EN	R/W	0b	External reference enable 0b = Disabled (default) 1b = Enabled
5	RESERVED	R/W	0b	Reserved always write 0b
4:2	OSR[2:0]	R/W	011b	Modulator oversampling ratio selection 000b = 128 001b = 256 010b = 512 011b = 1024 (default) 100b = 2048 101b = 4096 110b = 8192 111b = 16256
1:0	PWR	R/W	10b	Power mode selection 00b = Very-low-power 01b = Low-power 10b = High-resolution (default) 11b = High-resolution

8.6.5 GAIN1 Register (Address = 4h) [reset = 0000h]

The GAIN1 register is shown in Figure 8-30 and described in Table 8-18.

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Figure 8-30 GAIN1 Register

15	14	13	12	11	10	9	8
RESERVED	PGAGAIN3[2:0]			RESERVED	PGAGAIN2[2:0]
R/W-0b	R/W-000b			R/W-0b	R/W-000b

7	6	5	4	3	2	1	0
RESERVED	PGAGAIN1[2:0]			RESERVED	PGAGAIN0[2:0]
R/W-0b	R/W-000b			R/W-0b	R/W-000b

Table 8-18 GAIN1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0b	Reserved always write 0b
14:12	PGAGAIN3[2:0]	R/W	000b	PGA gain selection for channel 3 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128
11	RESERVED	R/W	0b	Reserved always write 0b
10:8	PGAGAIN2[2:0]	R/W	000b	PGA gain selection for channel 2 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128
7	RESERVED	R/W	0b	Reserved always write 0b
6:4	PGAGAIN1[2:0]	R/W	000b	PGA gain selection for channel 1 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128
3	RESERVED	R/W	0b	Reserved always write 0b
2:0	PGAGAIN0[2:0]	R/W	000b	PGA gain selection for channel 0 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128

8.6.6 GAIN2 Register (Address = 5h) [reset = 0000h]

The GAIN2 register is shown in Figure 8-31 and described in Table 8-19.

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Figure 8-31 GAIN2 Register

15	14	13	12	11	10	9	8
RESERVED	PGAGAIN7[2:0]			RESERVED	PGAGAIN6[2:0]
R-0b	R/W-000b			R-0b	R/W-000b

7	6	5	4	3	2	1	0
RESERVED	PGAGAIN5[2:0]			RESERVED	PGAGAIN4[2:0]
R/W-0b	R/W-000b			R/W-0b	R/W-000b

Table 8-19 GAIN2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0b	Reserved always write 0b
14:12	PGAGAIN7[2:0]	R/W	000b	PGA gain selection for channel 7 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128
11	RESERVED	R/W	0b	Reserved always write 0b
10:8	PGAGAIN6[2:0]	R/W	000b	PGA gain selection for channel 6 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128
7	RESERVED	R/W	0b	Reserved always write 0b
6:4	PGAGAIN5[2:0]	R/W	000b	PGA gain selection for channel 5 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b =128
3	RESERVED	R/W	0b	Reserved always write 0b
2:0	PGAGAIN4[2:0]	R/W	000b	PGA gain selection for channel 4 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128

8.6.7 CFG Register (Address = 06h) [reset = 0600h]

The CFG register is shown in Figure 8-32 and described in Table 8-20.

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Figure 8-32 CFG Register

15	14	13	12	11	10	9	8
RESERVED			GC_DLY[3:0]				GC_EN
R/W-000b			R/W-0011b				R/W-0b

7	6	5	4	3	2	1	0
CD_ALLCH	CD_NUM[2:0]			CD_LEN[2:0]			CD_EN
R/W-0b	R/W-000b			R/W-000b			R/W-0b

Table 8-20 CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15:13	RESERVED	R/W	000b	Reserved always write 000b
12:9	GC_DLY[3:0]	R/W	0011b	Global-chop delay selection Delay in modulator clock periods before measurement begins 0000b = 2 0001b = 4 0010b = 8 0011b = 16 (default) 0100b = 32 0101b = 64 0110b = 128 0111b = 256 1000b = 512 1001b = 1024 1010b = 2048 1011b = 4096 1100b = 8192 1101b = 16384 1110b = 32768 1111b = 65536
8	GC_EN	R/W	0b	Global-chop enable 0b = Disabled (default) 1b = Enabled
7	CD_ALLCH	R/W	0b	Current-detect channels selection Channels required to trigger current-detect 0b = Any channel (default) 1b = All channels
6:4	CD_NUM[2:0]	R/W	000b	Number of current-detect exceeded thresholds selection Number of current-detect exceeded thresholds to trigger a detection 000b = 1 (default) 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128
3:1	CD_LEN[2:0]	R/W	000b	Current-detect measurement length selection Current-detect measurement length in conversion periods 000b = 128 (default) 001b = 256 010b = 512 011b = 768 100b = 1280 101b = 1792 110b = 2560 111b = 3584
0	CD_EN	R/W	0b	Current-detect mode enable 0b = Disabled (default) 1b = Enabled

8.6.8 THRSHLD_MSB Register (Address = 07h) [reset = 0000h]

The THRSHLD_MSB register is shown in Figure 8-33 and described in Table 8-21.

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Figure 8-33 THRSHLD_MSB Register

15	14	13	12	11	10	9	8
CD_TH_MSB[23:16]
R/W-0000000000000000b

7	6	5	4	3	2	1	0
CD_TH_MSB[15:8]
R/W-0000000000000000b

Table 8-21 THRSHLD_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	CD_TH_MSB[23:8]	R/W	00000000 00000000b	Current-detect mode threshold register bits [23:8]. Value provided in two's complement format.

8.6.9 THRSHLD_LSB Register (Address = 08h) [reset = 0000h]

The THRSHLD_LSB register is shown in Figure 8-34 and described in Table 8-22.

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Figure 8-34 THRSHLD_LSB Register

15	14	13	12	11	10	9	8
CD_TH_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED				DCBLOCK[3:0]
R-0000b				R/W-0000b

Table 8-22 THRSHLD_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	CD_TH_LSB[7:0]	R/W	00000000b	Current-detect mode threshold register bits [7:0] Value provided in two's complement format
7:4	RESERVED	R	0000b	Reserved always reads 0000b
3:0	DCBLOCK[3:0]	R/W	0000b	DC Block filter setting See Table 8-4 for details

8.6.10 CH0_CFG Register (Address = 09h) [reset = 0000h]

The CH0_CFG register is shown in Figure 8-35 and described in Table 8-23.

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Figure 8-35 CH0_CFG Register

15	14	13	12	11	10	9	8
PHASE0[9:2]
R/W-0000000000b

7	6	5	4	3	2	1	0
PHASE0[1:0]		RESERVED			DCBLK0_DIS	MUX0[1:0]
R/W-0000000000b		R-000b			R/W-0b	R/W-00b

Table 8-23 CH0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15:6	PHASE0[9:0]	R/W	0000000000b	Channel 0 phase delay Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.
5:3	RESERVED	R	000b	Reserved always reads 000b
2	DCBLK0_DIS	R/W	0b	Channel 0 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel
1:0	MUX0[1:0]	R/W	00b	Channel 0 input selection 00b = AIN0P and AIN0N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal

8.6.11 CH0_OCAL_MSB Register (Address = 0Ah) [reset = 0000h]

The CH0_OCAL_MSB register is shown in Figure 8-36 and described in Table 8-24.

Return to the Summary Table.

Figure 8-36 CH0_OCAL_MSB Register

15	14	13	12	11	10	9	8
OCAL0_MSB[15:8]
R/W-0000000000000000b

7	6	5	4	3	2	1	0
OCAL0_MSB[7:0]
R/W-0000000000000000b

Table 8-24 CH0_OCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	OCAL0_MSB[15:0]	R/W	00000000 00000000b	Channel 0 offset calibration register bits [23:8]. Value provided in two's complement format.

8.6.12 CH0_OCAL_LSB Register (Address = 0Bh) [reset = 0000h]

The CH0_OCAL_LSB register is shown in Figure 8-37 and described in Table 8-25.

Return to the Summary Table.

Figure 8-37 CH0_OCAL_LSB Register

15	14	13	12	11	10	9	8
OCAL0_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-25 CH0_OCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	OCAL0_LSB[7:0]	R/W	00000000b	Channel 0 offset calibration register bits [7:0]. Value provided in two's complement format.
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.13 CH0_GCAL_MSB Register (Address = 0Ch) [reset = 8000h]

The CH0_GCAL_MSB register is shown in Figure 8-38 and described in Table 8-26.

Return to the Summary Table.

Figure 8-38 CH0_GCAL_MSB Register

15	14	13	12	11	10	9	8
GCAL0_MSB[15:8]
R/W-1000000000000000b

7	6	5	4	3	2	1	0
GCAL0_MSB[7:0]
R/W-1000000000000000b

Table 8-26 CH0_GCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	GCAL0_MSB	R/W	1000000000000000b	Channel 0 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴

8.6.14 CH0_GCAL_LSB Register (Address = 0Dh) [reset = 0000h]

The CH0_GCAL_LSB register is shown in Figure 8-39 and described in Table 8-27.

Return to the Summary Table.

Figure 8-39 CH0_GCAL_LSB Register

15	14	13	12	11	10	9	8
GCAL0_LSB
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-27 CH0_GCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	GCAL0_LSB[7:0]	R/W	00000000b	Channel 0 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.15 CH1_CFG Register (Address = 0Eh) [reset = 0000h]

The CH1_CFG register is shown in Figure 8-40 and described in Table 8-28.

Return to the Summary Table.

Figure 8-40 CH1_CFG Register

15	14	13	12	11	10	9	8
PHASE1[9:2]
R/W-0000000000b

7	6	5	4	3	2	1	0
PHASE1[1:0]		RESERVED			DCBLK1_DIS	MUX1
R/W-0000000000b		R-000b			R/W-0b	R/W-00b

Table 8-28 CH1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15:6	PHASE1[9:0]	R/W	0000000000b	Channel 1 phase delay Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.
5:3	RESERVED	R	000b	Reserved always reads 000b
2	DCBLK1_DIS	R/W	0b	Channel 1 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel
1:0	MUX1	R/W	00b	Channel 1 input selection 00b = AIN1P and AIN1N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal

8.6.16 CH1_OCAL_MSB Register (Address = 0Fh) [reset = 0000h]

The CH1_OCAL_MSB register is shown in Figure 8-41 and described in Table 8-29.

Return to the Summary Table.

Figure 8-41 CH1_OCAL_MSB Register

15	14	13	12	11	10	9	8
OCAL1_MSB[15:8]
R/W-0000000000000000b

7	6	5	4	3	2	1	0
OCAL1_MSB[7:0]
R/W-0000000000000000b

Table 8-29 CH1_OCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	OCAL1_MSB[15:0]	R/W	00000000 00000000b	Channel 1 offset calibration register bits [23:8] Value provided in two's complement format

8.6.17 CH1_OCAL_LSB Register (Address = 10h) [reset = 0000h]

The CH1_OCAL_LSB register is shown in Figure 8-42 and described in Table 8-30.

Return to the Summary Table.

Figure 8-42 CH1_OCAL_LSB Register

15	14	13	12	11	10	9	8
OCAL1_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-30 CH1_OCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	OCAL1_LSB[7:0]	R/W	00000000b	Channel 1 offset calibration register bits [7:0] Value provided in two's complement format
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.18 CH1_GCAL_MSB Register (Address = 11h) [reset = 8000h]

The CH1_GCAL_MSB register is shown in Figure 8-43 and described in Table 8-31.

Return to the Summary Table.

Figure 8-43 CH1_GCAL_MSB Register

15	14	13	12	11	10	9	8
GCAL1_MSB[15:8]
R/W-1000000000000000b

7	6	5	4	3	2	1	0
GCAL1_MSB[7:0]
R/W-1000000000000000b

Table 8-31 CH1_GCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	GCAL1_MSB[15:0]	R/W	1000000000000000b	Channel 1 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1)/2²⁴

8.6.19 CH1_GCAL_LSB Register (Address = 12h) [reset = 0000h]

The CH1_GCAL_LSB register is shown in Figure 8-44 and described in Table 8-32.

Return to the Summary Table.

Figure 8-44 CH1_GCAL_LSB Register

15	14	13	12	11	10	9	8
GCAL1_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-32 CH1_GCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	GCAL1_LSB[7:0]	R/W	00000000b	Channel 1 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.20 CH2_CFG Register (Address = 13h) [reset = 0000h]

The CH2_CFG register is shown in Figure 8-45 and described in Table 8-33.

Return to the Summary Table.

Figure 8-45 CH2_CFG Register

15	14	13	12	11	10	9	8
PHASE2[9:2]
R/W-0000000000b

7	6	5	4	3	2	1	0
PHASE2[1:0]		RESERVED			DCBLK2_DIS	MUX2
R/W-0000000000b		R-000b			R/W-0b	R/W-00b

Table 8-33 CH2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15:6	PHASE2[9:0]	R/W	0000000000b	Channel 2 phase delay Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.
5:3	RESERVED	R	000b	Reserved always reads 000b
2	DCBLK2_DIS	R/W	0b	Channel 2 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel
1:0	MUX2	R/W	00b	Channel 2 input selection 00b = AIN2P and AIN2N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal

8.6.21 CH2_OCAL_MSB Register (Address = 14h) [reset = 0000h]

The CH2_OCAL_MSB register is shown in Figure 8-46 and described in Table 8-34.

Return to the Summary Table.

Figure 8-46 CH2_OCAL_MSB Register

15	14	13	12	11	10	9	8
OCAL2_MSB[15:8]
R/W-0000000000000000b

7	6	5	4	3	2	1	0
OCAL2_MSB[7:0]
R/W-0000000000000000b

Table 8-34 CH2_OCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	OCAL2_MSB[15:0]	R/W	00000000 00000000b	Channel 2 offset calibration register bits [23:8] Value provided in two's complement format

8.6.22 CH2_OCAL_LSB Register (Address = 15h) [reset = 0000h]

The CH2_OCAL_LSB register is shown in Figure 8-47 and described in Table 8-35.

Return to the Summary Table.

Figure 8-47 CH2_OCAL_LSB Register

15	14	13	12	11	10	9	8
OCAL2_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-35 CH2_OCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	OCAL2_LSB[7:0]	R/W	00000000b	Channel 2 offset calibration register bits [7:0] Value provided in two's complement format
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.23 CH2_GCAL_MSB Register (Address = 16h) [reset = 8000h]

The CH2_GCAL_MSB register is shown in Figure 8-48 and described in Table 8-36.

Return to the Summary Table.

Figure 8-48 CH2_GCAL_MSB Register

15	14	13	12	11	10	9	8
GCAL2_MSB[15:8]
R/W-1000000000000000b

7	6	5	4	3	2	1	0
GCAL2_MSB[7:0]
R/W-1000000000000000b

Table 8-36 CH2_GCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	GCAL2_MSB[15:0]	R/W	1000000000000000b	Channel 2 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴

8.6.24 CH2_GCAL_LSB Register (Address = 17h) [reset = 0000h]

The CH2_GCAL_LSB register is shown in Figure 8-49 and described in Table 8-37.

Return to the Summary Table.

Figure 8-49 CH2_GCAL_LSB Register

15	14	13	12	11	10	9	8
GCAL2_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-37 CH2_GCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	GCAL2_LSB[7:0]	R/W	00000000b	Channel 2 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.25 CH3_CFG Register (Address = 18h) [reset = 0000h]

The CH3_CFG register is shown in Figure 8-50 and described in Table 8-38.

Return to the Summary Table.

Figure 8-50 CH3_CFG Register

15	14	13	12	11	10	9	8
PHASE3[9:2]
R/W-0000000000b

7	6	5	4	3	2	1	0
PHASE3[1:0]		RESERVED			DCBLK3_DIS	MUX3
R/W-0000000000b		R-000b			R/W-0b	R/W-00b

Table 8-38 CH3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15:6	PHASE3[9:0]	R/W	0000000000b	Channel 3 phase delay Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.
5:3	RESERVED	R	000b	Reserved always reads 00000000b
2	DCBLK3_DIS	R/W	0b	Channel 3 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel
1:0	MUX3	R/W	00b	Channel 3 input selection 00b = AIN3P and AIN3N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal

8.6.26 CH3_OCAL_MSB Register (Address = 19h) [reset = 0000h]

The CH3_OCAL_MSB register is shown in Figure 8-51 and described in Table 8-39.

Return to the Summary Table.

Figure 8-51 CH3_OCAL_MSB Register

15	14	13	12	11	10	9	8
OCAL3_MSB[15:8]
R/W-0000000000000000b

7	6	5	4	3	2	1	0
OCAL3_MSB[7:0]
R/W-0000000000000000b

Table 8-39 CH3_OCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	OCAL3_MSB[15:0]	R/W	00000000 00000000b	Channel 3 offset calibration register bits [23:8] Value provided in two's complement format

8.6.27 CH3_OCAL_LSB Register (Address = 1Ah) [reset = 0000h]

The CH3_OCAL_LSB register is shown in Figure 8-52 and described in Table 8-40.

Return to the Summary Table.

Figure 8-52 CH3_OCAL_LSB Register

15	14	13	12	11	10	9	8
OCAL3_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-40 CH3_OCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	OCAL3_LSB[7:0]	R/W	00000000b	Channel 3 offset calibration register bits [7:0] Value provided in two's complement format
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.28 CH3_GCAL_MSB Register (Address = 1Bh) [reset = 8000h]

The CH3_GCAL_MSB register is shown in Figure 8-53 and described in Table 8-41.

Return to the Summary Table.

Figure 8-53 CH3_GCAL_MSB Register

15	14	13	12	11	10	9	8
GCAL3_MSB[15:8]
R/W-1000000000000000b

7	6	5	4	3	2	1	0
GCAL3_MSB[7:0]
R/W-1000000000000000b

Table 8-41 CH3_GCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	GCAL3_MSB[15:0]	R/W	1000000000000000b	Channel 3 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴

8.6.29 CH3_GCAL_LSB Register (Address = 1Ch) [reset = 0000h]

The CH3_GCAL_LSB register is shown in Figure 8-54 and described in Table 8-42.

Return to the Summary Table.

Figure 8-54 CH3_GCAL_LSB Register

15	14	13	12	11	10	9	8
GCAL3_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-42 CH3_GCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	GCAL3_LSB[7:0]	R/W	00000000b	Channel 3 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.30 CH4_CFG Register (Address = 1Dh) [reset = 0000h]

The CH4_CFG register is shown in Figure 8-55 and described in Table 8-43.

Return to the Summary Table.

Figure 8-55 CH4_CFG Register

15	14	13	12	11	10	9	8
PHASE4[9:2]
R/W-0000000000b

7	6	5	4	3	2	1	0
PHASE4[1:0]		RESERVED			DCBLK4_DIS	MUX4
R/W-0000000000b		R-000b			R/W-0b	R/W-00b

Table 8-43 CH4_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15:6	PHASE4[9:0]	R/W	0000000000b	Channel 4 phase delay Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.
5:3	RESERVED	R	000b	Reserved always reads 000b
2	DCBLK4_DIS	R/W	0b	Channel 4 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel
1:0	MUX4	R/W	00b	Channel 4 input selection 00b = AIN4P and AIN4N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal

8.6.31 CH4_OCAL_MSB Register (Address = 1Eh) [reset = 0000h]

The CH4_OCAL_MSB register is shown in Figure 8-56 and described in Table 8-44.

Return to the Summary Table.

Figure 8-56 CH4_OCAL_MSB Register

15	14	13	12	11	10	9	8
OCAL4_MSB[15:8]
R/W-0000000000000000b

7	6	5	4	3	2	1	0
OCAL4_MSB[7:0]
R/W-0000000000000000b

Table 8-44 CH4_OCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	OCAL4_MSB[15:0]	R/W	00000000 00000000b	Channel 4 offset calibration register bits [23:8] Value provided in two's complement format

8.6.32 CH4_OCAL_LSB Register (Address = 1Fh) [reset = 0000h]

The CH4_OCAL_LSB register is shown in Figure 8-57 and described in Table 8-45.

Return to the Summary Table.

Figure 8-57 CH4_OCAL_LSB Register

15	14	13	12	11	10	9	8
OCAL4_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-45 CH4_OCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	OCAL4_LSB[7:0]	R/W	00000000b	Channel 4 offset calibration register bits [7:0] Value provided in two's complement format
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.33 CH4_GCAL_MSB Register (Address = 20h) [reset = 8000h]

The CH4_GCAL_MSB register is shown in Figure 8-58 and described in Table 8-46.

Return to the Summary Table.

Figure 8-58 CH4_GCAL_MSB Register

15	14	13	12	11	10	9	8
GCAL4_MSB[15:8]
R/W-1000000000000000b

7	6	5	4	3	2	1	0
GCAL4_MSB[7:0]
R/W-1000000000000000b

Table 8-46 CH4_GCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	GCAL4_MSB[15:0]	R/W	1000000000000000b	Channel 4 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴

8.6.34 CH4_GCAL_LSB Register (Address = 21h) [reset = 0000h]

The CH4_GCAL_LSB register is shown in Figure 8-59 and described in Table 8-47.

Return to the Summary Table.

Figure 8-59 CH4_GCAL_LSB Register

15	14	13	12	11	10	9	8
GCAL4_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-47 CH4_GCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	GCAL4_LSB[7:0]	R/W	00000000b	Channel 4 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.35 CH5_CFG Register (Address = 22h) [reset = 0000h]

The CH5_CFG register is shown in Figure 8-60 and described in Table 8-48.

Return to the Summary Table.

Figure 8-60 CH5_CFG Register

15	14	13	12	11	10	9	8
PHASE5[9:2]
R/W-0000000000b

7	6	5	4	3	2	1	0
PHASE5[1:0]		RESERVED			DCBLK5_DIS	MUX5
R/W-0000000000b		R-000b			R/W-0b	R/W-00b

Table 8-48 CH5_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15:6	PHASE5[9:0]	R/W	0000000000b	Channel 5 phase delay Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.
5:3	RESERVED	R	000b	Reserved always reads 000b
2	DCBLK5_DIS	R/W	0b	Channel 5 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel
1:0	MUX5	R/W	00b	Channel 5 put selection 00b = AIN5P and AIN5N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal

8.6.36 CH5_OCAL_MSB Register (Address = 23h) [reset = 0000h]

CH5_OCAL_MSB is shown in Figure 8-61 and described in Table 8-49.

Return to the Summary Table.

Figure 8-61 CH5_OCAL_MSB Register

15	14	13	12	11	10	9	8
OCAL5_MSB[15:8]
R/W-0000000000000000b

7	6	5	4	3	2	1	0
OCAL5_MSB[7:0]
R/W-0000000000000000b

Table 8-49 CH5_OCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	OCAL5_MSB[15:0]	R/W	00000000 00000000b	Channel 5 offset calibration register bits [23:8] Value provided in two's complement format

8.6.37 CH5_OCAL_LSB Register (Address = 24h) [reset = 0000h]

The CH5_OCAL_LSB register is shown in Figure 8-62 and described in Table 8-50.

Return to the Summary Table.

Figure 8-62 CH5_OCAL_LSB Register

15	14	13	12	11	10	9	8
OCAL5_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-50 CH5_OCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	OCAL5_LSB[7:0]	R/W	00000000b	Channel 5 offset calibration register bits [7:0] Value provided in two's complement format
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.38 CH5_GCAL_MSB Register (Address = 25h) [reset = 8000h]

The CH5_GCAL_MSB register is shown in Figure 8-63 and described in Table 8-51.

Return to the Summary Table.

Figure 8-63 CH5_GCAL_MSB Register

15	14	13	12	11	10	9	8
GCAL5_MSB[15:8]
R/W-1000000000000000b

7	6	5	4	3	2	1	0
GCAL5_MSB[7:0]
R/W-1000000000000000b

Table 8-51 CH5_GCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	GCAL5_MSB[15:0]	R/W	1000000000000000b	Channel 5 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴

8.6.39 CH5_GCAL_LSB Register (Address = 26h) [reset = 0000h]

The CH5_GCAL_LSB register is shown in Figure 8-64 and described in Table 8-52.

Return to the Summary Table.

Figure 8-64 CH5_GCAL_LSB Register

15	14	13	12	11	10	9	8
GCAL5_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-52 CH5_GCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	GCAL5_LSB[7:0]	R/W	00000000b	Channel 5 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.40 CH6_CFG Register (Address = 27h) [reset = 0000h]

The CH6_CFG register is shown in Figure 8-65 and described in Table 8-53.

Return to the Summary Table.

Figure 8-65 CH6_CFG Register

15	14	13	12	11	10	9	8
PHASE6[9:2]
R/W-0000000000b

7	6	5	4	3	2	1	0
PHASE6[1:0]		RESERVED			DCBLK6_DIS	MUX6
R/W-0000000000b		R-000b			R/W-0b	R/W-00b

Table 8-53 CH6_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15:6	PHASE6[9:0]	R/W	0000000000b	Channel 6 phase delay Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.
5:3	RESERVED	R	000b	Reserved always reads 000b
2	DCBLK6_DIS	R/W	0b	Channel 6 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel
1:0	MUX6	R/W	00b	Channel 6 input selection 00b = AIN6P and AIN6N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal

8.6.41 CH6_OCAL_MSB Register (Address = 28h) [reset = 0000h]

The CH6_OCAL_MSB register is shown in Figure 8-66 and described in Table 8-54.

Return to the Summary Table.

Figure 8-66 CH6_OCAL_MSB Register

15	14	13	12	11	10	9	8
OCAL6_MSB[15:8]
R/W-0000000000000000b

7	6	5	4	3	2	1	0
OCAL6_MSB[7:0]
R/W-0000000000000000b

Table 8-54 CH6_OCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	OCAL6_MSB[15:0]	R/W	00000000 00000000b	Channel 6 offset calibration register bits [23:8] Value provided in two's complement format

8.6.42 CH6_OCAL_LSB Register (Address = 29h) [reset = 0000h]

The CH6_OCAL_LSB register is shown in Figure 8-67 and described in Table 8-55.

Return to the Summary Table.

Figure 8-67 CH6_OCAL_LSB Register

15	14	13	12	11	10	9	8
OCAL6_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-55 CH6_OCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	OCAL6_LSB[7:0]	R/W	00000000b	Channel 6 offset calibration register bits [7:0] Value provided in two's complement format
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.43 CH6_GCAL_MSB Register (Address = 2Ah) [reset = 8000h]

The CH6_GCAL_MSB register is shown in Figure 8-68 and described in Table 8-56.

Return to the Summary Table.

Figure 8-68 CH6_GCAL_MSB Register

15	14	13	12	11	10	9	8
GCAL6_MSB[15:8]
R/W-1000000000000000b

7	6	5	4	3	2	1	0
GCAL6_MSB[7:0]
R/W-1000000000000000b

Table 8-56 CH6_GCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	GCAL6_MSB[15:0]	R/W	1000000000000000b	Channel 6 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴

8.6.44 CH6_GCAL_LSB Register (Address = 2Bh) [reset = 0000h]

The CH6_GCAL_LSB register is shown in Figure 8-69 and described in Table 8-57.

Return to the Summary Table.

Figure 8-69 CH6_GCAL_LSB Register

15	14	13	12	11	10	9	8
GCAL6_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-57 CH6_GCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	GCAL6_LSB[7:0]	R/W	00000000b	Channel 6 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.45 CH7_CFG Register (Address = 2Ch) [reset = 0000h]

The CH7_CFG register is shown in Figure 8-70 and described in Table 8-58.

Return to the Summary Table.

Figure 8-70 CH7_CFG Register

15	14	13	12	11	10	9	8
PHASE7[9:2]
R/W-0000000000b

7	6	5	4	3	2	1	0
PHASE7[1:0]		RESERVED			DCBLK7_DIS	MUX7
R/W-0000000000b		R-000b			R/W-0b	R/W-00b

Table 8-58 CH7_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15:6	PHASE7[9:0]	R/W	0000000000b	Channel 7 phase delay Phase delay in modulator clock cycles provided in two's complement format. See Table 8-5 for details.
5:3	RESERVED	R	000b	Reserved always reads 000b
2	DCBLK7_DIS	R/W	0b	Channel 7 DC Block filter disable 0b = Controlled by DCBLOCK[3:0] (default) 1b = Disabled for this channel
1:0	MUX7	R/W	00b	Channel 7 input selection 00b = AIN7P and AIN7N (default) 01b = ADC inputs shorted 10b = Positive DC test signal 11b = Negative DC test signal

8.6.46 CH7_OCAL_MSB Register (Address = 2Dh) [reset = 0000h]

The CH7_OCAL_MSB register is shown in Figure 8-71 and described in Table 8-59.

Return to the Summary Table.

Figure 8-71 CH7_OCAL_MSB Register

15	14	13	12	11	10	9	8
OCAL7_MSB[15:8]
R/W-0000000000000000b

7	6	5	4	3	2	1	0
OCAL7_MSB[7:0]
R/W-0000000000000000b

Table 8-59 CH7_OCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	OCAL7_MSB[15:0]	R/W	00000000 00000000b	Channel 7 offset calibration register bits [23:8] Value provided in two's complement format

8.6.47 CH7_OCAL_LSB Register (Address = 2Eh) [reset = 0000h]

The CH7_OCAL_LSB register is shown in Figure 8-72 and described in Table 8-60.

Return to the Summary Table.

Figure 8-72 CH7_OCAL_LSB Register

15	14	13	12	11	10	9	8
OCAL7_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-60 CH7_OCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	OCAL7_LSB[7:0]	R/W	00000000b	Channel 7 offset calibration register bits [7:0] Value provided in two's complement format
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.48 CH7_GCAL_MSB Register (Address = 2Fh) [reset = 8000h]

The CH7_GCAL_MSB register is shown in Figure 8-73 and described in Table 8-61.

Return to the Summary Table.

Figure 8-73 CH7_GCAL_MSB Register

15	14	13	12	11	10	9	8
GCAL7_MSB[15:8]
R/W-1000000000000000b

7	6	5	4	3	2	1	0
GCAL7_MSB[7:0]
R/W-1000000000000000b

Table 8-61 CH7_GCAL_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	GCAL7_MSB[15:0]	R/W	10000000 00000000b	Channel 7 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴

8.6.49 CH7_GCAL_LSB Register (Address = 30h) [reset = 0000h]

The CH7_GCAL_LSB register is shown in Figure 8-74 and described in Table 8-62.

Return to the Summary Table.

Figure 8-74 CH7_GCAL_LSB Register

15	14	13	12	11	10	9	8
GCAL7_LSB[7:0]
R/W-00000000b

7	6	5	4	3	2	1	0
RESERVED
R-00000000b

Table 8-62 CH7_GCAL_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	GCAL7_LSB[7:0]	R/W	00000000b	Channel 7 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0·(2²⁴ – 1) / 2²⁴
7:0	RESERVED	R	00000000b	Reserved always reads 00000000b

8.6.50 REGMAP_CRC Register (Address = 3Eh) [reset = 0000h]

The REGMAP_CRC register is shown in Figure 8-75 and described in Table 8-63.

Return to the Summary Table.

Figure 8-75 REGMAP_CRC Register

15	14	13	12	11	10	9	8
REG_CRC[15:8]
R-0000000000000000b

7	6	5	4	3	2	1	0
REG_CRC[7:0]
R-0000000000000000b

Table 8-63 REGMAP_CRC Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	REG_CRC[15:0]	R	00000000 00000000b	Register map CRC value

8.6.51 RESERVED Register (Address = 3Fh) [reset = 0000h]

The RESERVED register is shown in Figure 8-76 and described in Table 8-64.

Return to the Summary Table.

Figure 8-76 RESERVED Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0000000000000000b

7	6	5	4	3	2	1	0
RESERVED
R/W-0000000000000000b

Table 8-64 RESERVED Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	RESERVED	R/W	00000000 00000000b	Reserved Always write 0000000000000000b

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発注情報

8.6 Registers

8.6.1 ID Register (Address = 00h) [reset = 28xxh]

8.6.2 STATUS Register (Address = 01h) [reset = 0500h]

8.6.3 MODE Register (Address = 02h) [reset = 0510h]

8.6.4 CLOCK Register (Address = 03h) [reset = FF0Eh]

8.6.5 GAIN1 Register (Address = 4h) [reset = 0000h]

8.6.6 GAIN2 Register (Address = 5h) [reset = 0000h]

8.6.7 CFG Register (Address = 06h) [reset = 0600h]

8.6.8 THRSHLD_MSB Register (Address = 07h) [reset = 0000h]

8.6.9 THRSHLD_LSB Register (Address = 08h) [reset = 0000h]

8.6.10 CH0_CFG Register (Address = 09h) [reset = 0000h]

8.6.11 CH0_OCAL_MSB Register (Address = 0Ah) [reset = 0000h]

8.6.12 CH0_OCAL_LSB Register (Address = 0Bh) [reset = 0000h]

8.6.13 CH0_GCAL_MSB Register (Address = 0Ch) [reset = 8000h]

8.6.14 CH0_GCAL_LSB Register (Address = 0Dh) [reset = 0000h]

8.6.15 CH1_CFG Register (Address = 0Eh) [reset = 0000h]

8.6.16 CH1_OCAL_MSB Register (Address = 0Fh) [reset = 0000h]

8.6.17 CH1_OCAL_LSB Register (Address = 10h) [reset = 0000h]

8.6.18 CH1_GCAL_MSB Register (Address = 11h) [reset = 8000h]

8.6.19 CH1_GCAL_LSB Register (Address = 12h) [reset = 0000h]

8.6.20 CH2_CFG Register (Address = 13h) [reset = 0000h]

8.6.21 CH2_OCAL_MSB Register (Address = 14h) [reset = 0000h]

8.6.22 CH2_OCAL_LSB Register (Address = 15h) [reset = 0000h]

8.6.23 CH2_GCAL_MSB Register (Address = 16h) [reset = 8000h]

8.6.24 CH2_GCAL_LSB Register (Address = 17h) [reset = 0000h]

8.6.25 CH3_CFG Register (Address = 18h) [reset = 0000h]

8.6.26 CH3_OCAL_MSB Register (Address = 19h) [reset = 0000h]

8.6.27 CH3_OCAL_LSB Register (Address = 1Ah) [reset = 0000h]

8.6.28 CH3_GCAL_MSB Register (Address = 1Bh) [reset = 8000h]

8.6.29 CH3_GCAL_LSB Register (Address = 1Ch) [reset = 0000h]

8.6.30 CH4_CFG Register (Address = 1Dh) [reset = 0000h]

8.6.31 CH4_OCAL_MSB Register (Address = 1Eh) [reset = 0000h]

8.6.32 CH4_OCAL_LSB Register (Address = 1Fh) [reset = 0000h]

8.6.33 CH4_GCAL_MSB Register (Address = 20h) [reset = 8000h]

8.6.34 CH4_GCAL_LSB Register (Address = 21h) [reset = 0000h]

8.6.35 CH5_CFG Register (Address = 22h) [reset = 0000h]

8.6.36 CH5_OCAL_MSB Register (Address = 23h) [reset = 0000h]

8.6.37 CH5_OCAL_LSB Register (Address = 24h) [reset = 0000h]

8.6.38 CH5_GCAL_MSB Register (Address = 25h) [reset = 8000h]

8.6.39 CH5_GCAL_LSB Register (Address = 26h) [reset = 0000h]

8.6.40 CH6_CFG Register (Address = 27h) [reset = 0000h]

8.6.41 CH6_OCAL_MSB Register (Address = 28h) [reset = 0000h]

8.6.42 CH6_OCAL_LSB Register (Address = 29h) [reset = 0000h]

8.6.43 CH6_GCAL_MSB Register (Address = 2Ah) [reset = 8000h]

8.6.44 CH6_GCAL_LSB Register (Address = 2Bh) [reset = 0000h]

8.6.45 CH7_CFG Register (Address = 2Ch) [reset = 0000h]

8.6.46 CH7_OCAL_MSB Register (Address = 2Dh) [reset = 0000h]

8.6.47 CH7_OCAL_LSB Register (Address = 2Eh) [reset = 0000h]

8.6.48 CH7_GCAL_MSB Register (Address = 2Fh) [reset = 8000h]

8.6.49 CH7_GCAL_LSB Register (Address = 30h) [reset = 0000h]

8.6.50 REGMAP_CRC Register (Address = 3Eh) [reset = 0000h]

8.6.51 RESERVED Register (Address = 3Fh) [reset = 0000h]