SBAS578A May   2012  – January 2016 ADS4128

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: General
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Requirements: LVDS and CMOS Modes
    9. 7.9  Reset Timing Requirements
    10. 7.10 Typical Characteristics
    11. 7.11 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Migrating From the ADS6149 Family
      2. 8.3.2 Digital Functions and Low-Latency Mode
      3. 8.3.3 Gain for SFDR and SNR Trade-Off
      4. 8.3.4 Offset Correction
      5. 8.3.5 Power Down
        1. 8.3.5.1 Global Power-Down
        2. 8.3.5.2 Standby
        3. 8.3.5.3 Output Buffer Disable
        4. 8.3.5.4 Input Clock Stop
      6. 8.3.6 Power-Supply Sequence
      7. 8.3.7 Output Data Format
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Interface Modes
        1. 8.4.1.1 Output Interface
        2. 8.4.1.2 DDR LVDS Outputs
        3. 8.4.1.3 LVDS Output Data and Clock Buffers
        4. 8.4.1.4 Parallel CMOS Interface
        5. 8.4.1.5 CMOS Interface Power Dissipation
        6. 8.4.1.6 Input Over-Voltage Indication (OVR Pin)
    5. 8.5 Programming
      1. 8.5.1 Serial Register Readout
      2. 8.5.2 Serial Interface
        1. 8.5.2.1 Register Initialization
    6. 8.6 Register Maps
      1. 8.6.1 Serial Interface Register Map
      2. 8.6.2 Register Description
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
      2. 9.1.2 Driving Circuit
        1. 9.1.2.1 Drive Circuit Requirements
      3. 9.1.3 Analog Input
        1. 9.1.3.1 Input Common-Mode
      4. 9.1.4 Clock Input
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Sharing DRVDD and AVDD Supplies
    2. 10.2 Using DC/DC Power Supplies
    3. 10.3 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Supply Decoupling
      3. 11.1.3 Exposed Pad
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGZ Package(1)
48-Pin VQFN With Exposed Thermal Pad
LVDS Mode - Top View
ADS4128 po_lvds_412x_bas483.gif
The thermal pad is connected to DRGND.

Pin Functions - LVDS Mode

PIN I/O DESCRIPTION
NAME NO.
AGND 9, 12, 14, 17, 19, 25 I Analog ground
AVDD 8, 18, 20, 22, 24, 26 I 1.8-V analog power supply
CLKM 11 I Differential clock input, negative
CLKP 10 I Differential clock input, positive
CLKOUTM 4 O Differential output clock, negative
CLKOUTP 5 O Differential output clock, positive
D0_D1_P 38 O Differential output data D0 and D1 multiplexed, true
D0_D1_M 37 O Differential output data D0 and D1 multiplexed, complement
D2_D3_P 40 O Differential output data D2 and D3 multiplexed, true
D2_D3_M 39 O Differential output data D2 and D3 multiplexed, complement
D4_D5_P 42 O Differential output data D4 and D5 multiplexed, true
D4_D5_M 41 O Differential output data D4 and D5 multiplexed, complement
D6_D7_P 44 O Differential output data D6 and D7 multiplexed, true
D6_D7_M 43 O Differential output data D6 and D7 multiplexed, complement
D8_D9_P 46 O Differential output data D8 and D9 multiplexed, true
D8_D9_M 45 O Differential output data D8 and D9 multiplexed, complement
D10_D11_P 48 O Differential output data D10 and D11 multiplexed, true
D10_D11_M 47 O Differential output data D10 and D11 multiplexed, complement
DFS 6 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS and CMOS output interface type. See Table 9 for detailed information.
DRGND 1, 36, PAD I Digital and output buffer ground
DRVDD 2, 35 I 1.8-V digital and output buffer supply
INM 16 I Differential analog input, negative
INP 15 I Differential analog input, positive
NC 21, 31, 32, 33, 34 — Do not connect
OE 7 I Output buffer enable input, active high; this pin has an internal 180-kΩ pull-up resistor to DRVDD.
OVR_SDOUT 3 O This pin functions as an out-of-range indicator after reset when register bit
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
RESERVED 23 I Digital control pin, reserved for future use
RESET 30 I Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin.
RESET has an internal 180-kΩ pull-down resistor.
SCLK 29 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and should be tied to ground.
This pin has an internal 180-kΩ pull-down resistor.
SDATA 28 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 11).
This pin has an internal 180-kΩ pull-down resistor.
SEN 27 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and should be tied to AVDD.
This pin has an internal 180-kΩ pull-up resistor to AVDD.
VCM 13 O Outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins.
RGZ Package(2)
48-Pin VQFN With Exposed Thermal Pad
CMOS - Top View
ADS4128 po_cmos_412x_bas483.gif
The thermal pad is connected to DRGND.

Pin Functions - CMOS Mode

PIN I/O DESCRIPTION
NAME NO.
AGND 9, 12, 14, 17, 19, 25 I Analog ground
AVDD 8, 18, 20, 22, 24, 26 I 1.8-V analog power supply
CLKM 11 I Differential clock input, negative
CLKP 10 I Differential clock input, positive
CLKOUT 5 O CMOS output clock
D0 37 O 12-bit CMOS output data
D1 38 O 12-bit CMOS output data
D2 39 O 12-bit CMOS output data
D3 40 O 12-bit CMOS output data
D4 41 O 12-bit CMOS output data
D5 42 O 12-bit CMOS output data
D6 43 O 12-bit CMOS output data
D7 44 O 12-bit CMOS output data
D8 45 O 12-bit CMOS output data
D9 46 O 12-bit CMOS output data
D10 47 O 12-bit CMOS output data
D11 48 O 12-bit CMOS output data
DFS 6 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS and CMOS output interface type. See Table 9 for detailed information.
DRGND 1, 36, PAD I Digital and output buffer ground
DRVDD 2, 35 I 1.8-V digital and output buffer supply
INP 15 I Differential analog input, positive
INM 16 I Differential analog input, negative
NC 21, 31, 32, 33, 34 — Do not connect
OE 7 I Output buffer enable input, active high; this pin has an internal 180-kΩ pull-up resistor to DRVDD.
OVR_SDOUT 3 O This pin functions as an out-of-range indicator after reset when register bit
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
RESET 30 I Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin.
RESET has an internal 180-kΩ pull-down resistor.
RESERVED 23 I Digital control pin, reserved for future use
SCLK 29 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and should be tied to ground.
This pin has an internal 180-kΩ pull-down resistor.
SDATA 28 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 11).
This pin has an internal 180-kΩ pull-down resistor.
SEN 27 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and should be tied to AVDD.
This pin has an internal 180-kΩ pull-up resistor to AVDD.
UNUSED 4 — Unused pin in CMOS mode
VCM 13 O Outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins.