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ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC
SBAS534E
July 2011 – January 2016
ADS4249
PRODUCTION DATA.
CONTENTS
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ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC
1
Features
2
Applications
3
Description
4
Revision History
5
ADS424x, ADS422x Family Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics: ADS4249 (250 MSPS)
7.6
Electrical Characteristics: General
7.7
Digital Characteristics
7.8
LVDS and CMOS Modes Timing Requirements
7.9
LVDS Timings at Lower Sampling Frequencies
7.10
CMOS Timings at Lower Sampling Frequencies
7.11
Serial Interface Timing Characteristics
7.12
Reset Timing (Only when Serial Interface is Used)
7.13
Typical Characteristics
7.13.1
Typical Characteristics: ADS4249
7.13.2
Typical Characteristics: Contour
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Digital Functions
8.3.2
Gain for SFDR, SNR Trade-Off
8.3.3
Offset Correction
8.3.4
Power-Down
8.3.4.1
Global Power-Down
8.3.4.2
Channel Standby
8.3.4.3
Input Clock Stop
8.3.5
Output Data Format
8.4
Device Functional Modes
8.4.1
Output Interface Modes
8.4.1.1
Output Interface
8.4.1.2
DDR LVDS Outputs
8.4.1.3
LVDS Buffer
8.4.1.4
Parallel CMOS Interface
8.4.1.5
CMOS Interface Power Dissipation
8.4.1.6
Multiplexed Mode of Operation
8.5
Programming
8.5.1
Parallel Configuration Only
8.5.2
Serial Interface Configuration Only
8.5.3
Using Both Serial Interface and Parallel Controls
8.5.4
Parallel Configuration Details
8.5.5
Serial Interface Details
8.5.5.1
Register Initialization
8.5.5.2
Serial Register Readout
8.6
Register Maps
8.6.1
Serial Register Map
8.6.2
Description of Serial Registers
8.6.2.1
Register Address 00h (Default = 00h)
8.6.2.2
Register Address 01h (Default = 00h)
8.6.2.3
Register Address 01h (Default = 00h)
8.6.2.4
Register Address 25h (Default = 00h)
8.6.2.5
Register Address 29h (Default = 00h)
8.6.2.6
Register Address 2Bh (Default = 00h)
8.6.2.7
Register Address 3Dh (Default = 00h)
8.6.2.8
Register Address 3Fh (Default = 00h)
8.6.2.9
Register Address 40h (Default = 00h)
8.6.2.10
Register Address 41h (Default = 00h)
8.6.2.11
Register Address 42h (Default = 00h)
8.6.2.12
Register Address 45h (Default = 00h)
8.6.2.13
Register Address 4Ah (Default = 00h)
8.6.2.14
Register Address 58h (Default = 00h)
8.6.2.15
Register Address BFh (Default = 00h)
8.6.2.16
Register Address C1h (Default = 00h)
8.6.2.17
Register Address CFh (Default = 00h)
8.6.2.18
Register Address EFh (Default = 00h)
8.6.2.19
Register Address F1h (Default = 00h)
8.6.2.20
Register Address F2h (Default = 00h)
8.6.2.21
Register Address 2h (Default = 00h)
8.6.2.22
Register Address D5h (Default = 00h)
8.6.2.23
Register Address D7h (Default = 00h)
8.6.2.24
Register Address DBh (Default = 00h)
9
Application and Implementation
9.1
Application Information
9.1.1
Theory of Operation
9.1.2
Analog Input
9.1.2.1
Drive Circuit Requirements
9.1.2.2
Driving Circuit
9.1.3
Clock Input
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Analog Input
9.2.2.2
Common Mode Voltage Output (VCM)
9.2.2.3
Clock Driver
9.2.2.4
Digital Interface
9.2.3
Application Curve
10
Power Supply Recommendations
10.1
Sharing DRVDD and AVDD Supplies
10.2
Using DC-DC Power Supplies
10.3
Power Supply Bypassing
11
Layout
11.1
Layout Guidelines
11.1.1
Grounding
11.1.2
Exposed Pad
11.1.3
Routing Analog Inputs
11.1.4
Routing Digital Inputs
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.1.1.1
Definition of Specifications
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RGC|64
MPQF125F
サーマルパッド・メカニカル・データ
RGC|64
QFND123N
発注情報
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