Table 35. ADS42LBx9 Design Requirements

9.2.2.1 Analog Input

The analog input pins have analog buffers (running from the AVDD3V supply) that internally drive the differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external driving source (at dc, a 10-kΩ differential input resistance is provided in shunt with a 4-pF differential input capacitance). The buffer helps isolate the external driving source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier than when compared to an ADC without the buffer.

The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-V_PP differential input swing. When programmed for 2.5-V_PP full-scale, each input pin must swing symmetrically between VCM + 0.625 V and VCM – 0.625 V.

The input sampling circuit has a high 3-dB bandwidth that extends up to 900 MHz (measured with a 50-Ω source driving a 50-Ω termination between INP and INM). The dynamic offset of the first-stage sub-ADC limits the maximum analog input frequency to approximately 250 MHz (with a 2.5-V_PP full-scale amplitude) and to approximately 400 MHz (with a 2-V_PP full-scale amplitude). This maximum analog input frequency is different than the analog bandwidth of 900 MHz, which is only an indicator of signal amplitude versus frequency.

9.2.2.1.1 Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This technique improves the common-mode noise immunity and even-order harmonic rejection. A small resistor (10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics.

Figure 110, Figure 111, and Figure 112 show the differential impedance (Z_IN = R_IN || C_IN) at the ADC input pins. The presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz.

1.

NOINDENT:

X = A or B.

2.

NOINDENT:

Z_IN = R_IN || (1 / jωC_IN).

Figure 110. ADC Equivalent Input Impedance

Figure 111. ADC Analog Input Resistance (R_IN) Across Frequency

Figure 112. ADC Analog Input Capacitance (C_IN) Across Frequency

9.2.2.1.2 Driving Circuit

An example driving circuit configuration is shown in Figure 113. To optimize even-harmonic performance at high input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended, as shown in Figure 113. Note that the drive circuit is terminated by 50 Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage. If HD2 optimization is a concern, using a 10-Ω series resistor on the INP side and a 9.5-Ω series resistor on the INM side may help improve HD2 by 2 dB to 3 dB at a 85-dBFS level on a 170-MHz IF. An additional R-C-R (39 Ω - 6.8 pF - 39 Ω) circuit placed near device pins helps further improve HD3.

Figure 113. Drive Circuit for Input Frequencies up to 250 MHz

The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 113. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω source impedance). For high input frequencies (>250MHz), the R-C-R circuit can be removed as indicated in Figure 114.

Figure 114. Drive Circuit for Input Frequencies > 250 MHz

9.2.2.1.3 Using the ADS42LBx9 In Time-Domain, Low-Frequency Pulse Applications

The analog buffers inside the device are implemented to provide excellent linearity over a wide range of frequencies. However, at very low frequencies (< 100 kHz) the buffer presents a high-pass response, as shown in Figure 115 and Figure 116. This response does not affect most frequency-domain applications, but can require compensation techniques for time-domain, dc-coupled applications. Application report SBAA220 discusses simple techniques to compensate for the analog buffer response.

Figure 115. Analog Buffer in the ADS42LBx9

Figure 116. Buffer Response at Very Low Input Frequencies

9.2.2.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADS42LB69 and ADS42LB49 can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 117, Figure 118, and Figure 119. Figure 119 details the internal clock buffer.

NOTE:

R_T = termination resistor, if necessary.

Figure 117. Differential Sine-Wave Clock Driving Circuit

Figure 118. LVDS Clock Driving Circuit

Figure 119. LVPECL Clock Driving Circuit

NOTE:

C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 120. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 121. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

Figure 121. Single-Ended Clock Driving Circuit

9.2.2.3 SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 3. Quantization noise is typically not noticeable in pipeline converters and is 96 dBFS for a 16-bit ADC. Thermal noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies.

Equation 3.

SNR limitation is a result of sample clock jitter and can be calculated by Equation 4:

Equation 4.

The total clock jitter (T_Jitter) has three components: the internal aperture jitter (85 f_S for the device) is set by the noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. T_Jitter can be calculated by Equation 5:

Equation 5.

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input while a faster clock slew rate improves ADC aperture jitter. The device has a 74.1-dBFS thermal noise and an 85-f_S internal aperture jitter. The SNR value depends on the amount of external jitter for different input frequencies, as shown in Figure 122.

Figure 122. SNR versus Input Frequency and External Clock Jitter