ADS5474 14-Bit, 400-MSPS Analog-to-Digital Converter
- SLAS525D July 2007 – December 2017 ADS5474
  
  PRODUCTION DATA.

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DATA SHEET

ADS5474 14-Bit, 400-MSPS Analog-to-Digital Converter

1 Features

400-MSPS Sample Rate
14-Bit Resolution, 11.2-Bits ENOB
1.4-GHz Input Bandwidth
80-dBc SFDR at 230 MHz and 400 MSPS
69.8-dBFS SNR at 230 MHz and 400 MSPS
2.2-V_PP Differential Input Voltage
LVDS-Compatible Outputs
2.5-W Total Power Dissipation
50-mW Power-Down Mode
Offset Binary Output Format
Output Data Transitions on the Rising and Falling Edges of a Half-Rate Output Clock
On-Chip Analog Buffer, Track-and-Hold, and Reference Circuit
HTQFP-80 PowerPAD™ Package
(14-mm × 14-mm Footprint)
Industrial Temperature Range:
–40°C to +85°C
Pin-Similar, -Compatible With 12-, 13-, and 14-Bit Family: ADS5463, ADS5440, ADS5444

2 Applications

Test and Measurement Instrumentation
Software-Defined Radio
Data Acquisition
Power Amplifier Linearization
Communication Instrumentation
Radar

3 Description

The ADS5474 device is a 14-bit, 400-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. This ADC is one of a family of 12-, 13-, and 14-bit ADCs that operate from 210 MSPS to 500 MSPS. The ADS5474 device has an input buffer that isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design.

Designed with a 1.4-GHz input bandwidth for the conversion of wide-bandwidth signals that exceed 400 MHz of input frequency at 400 MSPS, the ADS5474 device has outstanding low-noise performance and spurious-free dynamic range over a large input frequency range.

The ADS5474 device is available in an TQFP-80 PowerPAD package. The device is built on Texas Instruments complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to +85°C).

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
ADS5474	HTQFP (80)	12.00 mm x 12.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

4 Revision History

Changes from C Revision (January 2016) to D Revision

Changed CLK input sample rate (sine wave) parameter maximum specification from 400 MSPS to 404 MSPS Go
Changed max sample rate from 400 MHz to 404 MHz in Detailed Design Procedure sectionGo

Changes from B Revision (February 2012) to C Revision

Added ESD Ratings table, Feature Description section, Device Functional Modessection, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from A Revision (August 2008) to B Revision

Changed 1.6pF to 2.3pF TYP Input capacitance in ELECTRICAL CHARACTERISTICSGo
Changed (where DRY equals the CLK frequency) to (where DRY equals ½ the CLK frequency) in Digital Outputs sectionGo

5 Pin Configuration and Functions

PFP Package

80-Pin HTQFP With PowerPAD

Top View

1. NC - No internal connection.

Pin Functions

PIN			DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
AIN	16	I	Differential input signal (positive)
AIN	17	I	Differential input signal (negative)
AVDD5	3		Analog power supply (5 V)
	8
	13
	14
	19
	21
	23
	25
	27
	31
AVDD3	35		Analog power supply (3.3 V) (suggestion for ≤ 250 MSPS: leave option to connect to 5 V for ADS5440, ADS5444 13-bit compatibility)
	37
	39
DVDD3	1		Digital and output driver power supply (3.3 V)
	51
	66
AGND	7		Analog Ground
	9
	12
	15
	18
	20
	22
	24
	26
	28
	30
	32
	34
	36
	38
	40
DGND	2		Digital Ground
	52
	65
CLK	10	I	Differential input clock (positive). Conversion is initiated on rising edge, digital outputs on falling edge.
CLK	11	I	Differential input clock (negative)
D0	48	O	LVDS digital output pair, least significant bit (LSB)
D0	47	O	LVDS digital output pair, least significant bit (LSB)
D1	50	O	LVDS digital output pairs
D1	49
D2	54
D2	53
D3	56
D3	55
D4	58
D4	57
D5	60
D5	59
D6	62
D6	61
D7	64
D7	63
D8	68
D8	67
D9	70
D9	69
D10	72
D10	71
D11	74
D11	73
D12	76
D12	75
D13	78	O	LVDS digital output pair, most significant bit (MSB)
D13	77	O	LVDS digital output pair, most significant bit (MSB)
DRY	80	O	Data ready LVDS output pair
DRY	79	O	Data ready LVDS output pair
NC	4	-	No connection (pins 4 and 5 should be left floating)
	5	-	No connection (pins 4 and 5 should be left floating)
	43	-	No connection (pins 43 to 46 are possible future bit additions for this pinout and therefore can be connected to a digital bus or left floating)
	44
	45
	46
OVR	42	O	Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range.
OVR	41	O
VCM	29	O	Common-mode voltage output (3.1 V nominal). Commonly used in DC-coupled applications to set the input signal to the correct common-mode voltage. A 0.1-μF capacitor from VCM to AGND is recommended, but not required. (This pin is not used on the ADS5440, ADS5444, and ADS5463)
PWD	33		Power-down (active high). Device is in sleep mode when PWD pin is logic HIGH. ADC converter is awake when PWD is logic LOW (grounded). (This pin is not used on the ADS5440, ADS5444, and ADS5463)
VREF	6		Reference voltage input/output (2.4 V nominal). A 0.1-μF capacitor from VREF to AGND is recommended, but not required.
(Power Pad)	(not numbered)		Power Pad for thermal relief, also Analog Ground