8.2.2.1 Clocking Source for ADC5474

The signal to noise ratio of the ADC is limited by three different factors: the quantization noise, the thermal noise, and the total jitter of the sample clock. Quantization noise is driven by the resolution of the ADC, which is 14 bits for the ADS5474. Thermal noise is typically not noticeable in high speed pipelined converters such as the ADS5474, but may be estimated by looking at the signal to noise ratio of the ADC with very low input frequencies and using Equation 1 to solve for thermal noise. (For this estimation, we will look to the ADS5474 datasheet and take the specified SNR for the lowest frequency listed. The lowest input frequency listed for the ADS5474 is at 30 MHz, and the SNR at that frequency is 70.3 dB, so we will use 70.3 dB as our SNR limit due to thermal noise. This is just an approximation, and the lower the input frequency that has an SNR specification the better this approximation would be.) The thermal noise limits the SNR at low input frequencies while the clock jitter sets the SNR for higher input frequencies.

Quantization noise is also a limiting factor for SNR, as the theoretical maximum achievable SNR as a function of the number of bits of resolution is set by Equation 1.

Equation 1.

where

• N = number of bits resolution

For a 14-bit ADC, the maximum SNR = 1.76 + (6.02 × 14) = 86.04 dB. This is the number that we shall enter into Equation 2 for quantization noise as we solve for total SNR for different amounts of clock jitter using Equation 2.

Equation 2.

The SNR limitation due to sample clock jitter can be calculated using Equation 3:

Equation 3.

The clock jitter in Equation 3 is the total amount of clock jitter, whether the jitter source is internal to the ADC itself or external due to the clocking source. The total clock jitter (t_Jitter) has two components – the internal aperture jitter (103 fs for ADS5474) which is set by the noise of the clock input buffer, and the external clock jitter from the clocking source and all associated buffering of the clock signal. Total clock jitter can be calculated from the aperture jitter and the external clock jitter as in Equation 4.

Equation 4.

External clock jitter can be minimized by using high quality clock sources and jitter cleaners as well as bandpass filters at the clock input while a faster clock slew rate may at times also improve the ADC aperture jitter slightly.

The ADS5474 has an internal aperture jitter of 103 fs, which is largely fixed. The SNR depending on the amount of external jitter for different input frequencies is shown in Figure 45. Often the design requirements will list a target SNR for a system, and Equation 1 through Equation 3 are then used to calculate the external clock jitter needed from the clocking solution to meet the system objectives.

Figure 45 shows that with an external clock jitter of 100 fs rms, the expected SNR of the ADS5474 would be greater than 69 dBFS at an input tone of 200 MHz, which is the Nyquist limit. Having less external clock jitter such as 35 fs rms or even 50 fs rms would result in an SNR that would exceed our design target, but at possibly the expense of a more costly clocking solution. Having external clock jitter of 150 fs rms or more would fail to meet the design target.

8.2.2.2 Amplifier Selection

The amplifier and any input filtering will have its own SNR performance, and the SNR performance of the amplifier front end will combine with the SNR of the ADC itself to yield a system SNR that is less than that of the ADC itself. System SNR can be calculated from the SNR of the amplifier conditioning circuit and the overall ADC SNR as in Equation 5. In Equation 5, the SNR of the ADC would be the value derived from the datasheet specifications and the clocking derivation presented in the previous section.

Equation 5.

The signal-to-noise ratio (SNR) of the amplifier and filter can be calculated from the noise specifications in the datasheet for the amplifier, the amplitude of the signal, and the bandwidth of the filter. The noise from the amplifier is band-limited by the filter and the rolloff of the filter will depend on the order of the filter, therefore the user should replace the filter rolloff with an equivalent brick-wall filter bandwidth. For example, a first order filter may be approximated by a brick-wall filter with bandwidth of 1.57 times the bandwidth of the first order filter. We will assume a first order filter for this design. The amplifier and filter noise can be calculated using Equation 6:

Equation 6.

where

• E_FILTEROUT = E_NAMPOUT × √ENB
• E_NAMPOUT = the output noise density of the LMH3401 (3.4 nV / √Hz)
• ENB = the brick-wall equivalent noise bandwidth of the filter
• VO = the amplifier output signal. (which will be full scale input of the ADC expressed in rms)

In Equation 6, the parameters of the equation can be seen to be in terms of signal amplitude in the numerator and amplifier noise in the denominator, or SNR. For the numerator, use the full scale voltage specification of the ADS5474, or 2.2 V peal to peak differential. Because Equation 6 requires the signal voltage to be in rms, convert 2.2 V p-p to 0.7766 V rms.

The noise specification for the LMH3401 is listed as 3.4 (nV/√Hz), so we will use this value to integrate the noise component from DC out to the filter cutoff, using the equivalent brick wall filter of 200 MHz × 1.57, or 314 MHz. 3.4 (nV/√Hz) × 314 MHz yields 60248 nV, or 60.25 µV.

Using 0.7766 V rms for V_O and 60.25 µV for E_filterout, the SNR of the amplifier and filter as given by Equation 6 is approximately 82.2 dB.

Taking the SNR of the ADC as 69.2 dB from Figure 45, and SNR of the amplifier and filter as 82.2 dB, Equation 5 predicts the system SNR to be 68.99 dB. In other words, the SNR of the ADC and the SNR of the front end combine as the square root of the sum of squares, and since the SNR of the amplifier front end is seen to be much greater than the SNR of the ADC in this example, the SNR of the ADC dominates Equation 5 and the system SNR is seen to be nearly the SNR of the ADC itself. We assumed our design requirement to be 69 dB, and after a clocking solution was chosen and an amplifier, filter solution was chosen we have a predicted SNR of 68.99 dB. If we deem 68.99 dB to not be close enough, or wish to have some margin in the design, then either improving the clock jitter from 100 fs to 50 fs, or replacing the first order filter with a second order filter would get the predicted system SNR above the 69-dB design requirement.