SLAS525 Data sheet

6.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted.⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	AVDD5 to GND		6	V
	AVDD3 to GND		5
	DVDD3 to GND		5
Analog input to GND	Valid when supplies are on and within normal ranges. See additional information in the Power Supplies portion of the applications information in the back of the datasheet regarding Clock and Analog Inputs when the supplies are off.	–0.3	(AVDD5 + 0.3)	V
Clock input to GND		–0.3	(AVDD5 + 0.3)	V
CLK to CLK		–2.5	2.5	V
Digital data output to GND		–0.3	(DVDD3 + 0.3)	V
Operating temperature range		–40	85	°C
Maximum junction temperature			+150	°C
Storage temperature range		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
SUPPLIES
AVDD5	Analog supply voltage	4.75	5	5.25	V
AVDD3	Analog supply voltage	3.1	3.3	3.6	V
DVDD3	Output driver supply voltage	3	3.3	3.6	V
ANALOG INPUT
	Differential input range		2.2		V_PP
VCM	Input common mode		3.1		V
DIGITAL OUTPUT (DRY, DATA, OVR)
	Maximum differential output load		10		pF
CLOCK INPUT (CLK)
	CLK input sample rate (sine wave)	20		404	MSPS
	Clock amplitude, differential sine wave (see Figure 37)	0.5		5	V_PP
	Clock duty cycle (see Figure 31)	40%	50%	60%
T_A	Operating free-air temperature	–40		+85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS5474	UNIT
		PFP (HTQFP)
		80 PINS
R_θJA	Junction-to-ambient thermal resistance	25.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	7.6	°C/W
R_θJB	Junction-to-board thermal resistance	9.8	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	9.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Typical values at T_A = 25°C: minimum and maximum values over full temperature range T_MIN = –40°C to T_MAX = 85°C, sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input, and 3-V_PP differential clock, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Resolution				14		Bits
ANALOG INPUTS
	Differential input range			2.2		V_PP
	Analog input common-mode voltage	Self-biased; see VCM specification below		3.1		V
	Input resistance (dc)	Each input to VCM		500		Ω
	Input capacitance	Each input to GND		2.3		pF
	Analog input bandwidth (–3dB)			1.44		GHz
CMRR	Common-mode rejection ratio	Common-mode signal < 50 MHz (see Figure 27)		100		dB
INTERNAL REFERENCE VOLTAGE
VREF	Reference voltage			2.4		V
VCM	Analog input common-mode voltage reference output	With internal VREF. Provided as an output via the VCM pin for dc-coupled applications. If an external VREF is used, the VCM pin tracks as illustrated in Figure 42	2.9	3.1	3.3	V
	VCM temperature coefficient			–0.8		mV/°C
DYNAMIC ACCURACY
	No missing codes			Assured
DNL	Differential linearity error	f_IN = 70 MHz	–0.99	±0.7	1.5	LSB
INL	Integral linearity error	f_IN = 70 MHz	–3	±1	3	LSB
	Offset error		–11		11	mV
	Offset temperature coefficient			0.02		mV/°C
	Gain error		–5		5	%FS
	Gain temperature coefficient			–0.02		%FS/°C
POWER SUPPLY
I_AVDD5	5-V analog supply current	V_IN = full-scale, f_IN = 70 MHz, f_S = 400 MSPS		338	372	mA
I_AVDD3	3.3-V analog supply current	V_IN = full-scale, f_IN = 70 MHz, f_S = 400 MSPS		185	201	mA
I_DVDD3	3.3-V digital supply current (includes LVDS)	V_IN = full-scale, f_IN = 70 MHz, f_S = 400 MSPS		75	83	mA
	Total power dissipation			2.5	2.797	W
	Power-up time	From turn-on of AVDD5		50		μs
	Wake-up time	From PWD pin switched from HIGH (PWD active) to LOW (ADC awake) (see Figure 28)		5		μs
	Power-down power dissipation	PWD pin = logic HIGH		50	350	mW
PSRR	Power-supply rejection ratio, AVDD5 supply	Without 0.1-μF board supply capacitors, with < 1-MHz supply noise (see Figure 46)		75		dB
PSRR	Power-supply rejection ratio, AVDD3 supply	Without 0.1-μF board supply capacitors, with < 1-MHz supply noise (see Figure 46)		90		dB
PSRR	Power-supply rejection ratio, DVDD3 supply	Without 0.1-μF board supply capacitors, with < 1-MHz supply noise (see Figure 46)		110		dB
DYNAMIC AC CHARACTERISTICS
SNR	Signal-to-noise ratio	f_IN = 30 MHz		70.3		dBFS
		f_IN = 70 MHz	68.3	70.2
		f_IN = 130 MHz		70.1
		f_IN = 230 MHz	68	69.8
		f_IN = 351 MHz		69.1
		f_IN = 451 MHz		68.4
		f_IN = 651 MHz		67.5
		f_IN = 751 MHz		66.6
		f_IN = 999 MHz		64.7
SFDR	Spurious-free dynamic range	f_IN = 30 MHz		88		dBc
		f_IN = 70 MHz	74	86
		f_IN = 130 MHz		80
		f_IN = 230 MHz	71	80
		f_IN = 351 MHz		76
		f_IN = 451 MHz		71
		f_IN = 651 MHz		60
		f_IN = 751 MHz		55
		f_IN = 999 MHz		46
HD2	Second-harmonic	f_IN = 30 MHz		89		dBc
		f_IN = 70 MHz		87
		f_IN = 130 MHz		90
		f_IN = 230 MHz		84
		f_IN = 351 MHz		76
		f_IN = 451 MHz		71
		f_IN = 651 MHz		74
		f_IN = 751 MHz		70
		f_IN = 999 MHz		55
HD3	Third-harmonic	f_IN = 30 MHz		93		dBc
		f_IN = 70 MHz		86
		f_IN = 130 MHz		80
		f_IN = 230 MHz		80
		f_IN = 351 MHz		85
		f_IN = 451 MHz		71
		f_IN = 651 MHz		60
		f_IN = 751 MHz		55
		f_IN = 999 MHz		46
	Worst harmonic, spur (other than HD2 and HD3)	f_IN = 30 MHz		95		dBc
		f_IN = 70 MHz		93
		f_IN = 130 MHz		85
		f_IN = 230 MHz		85
		f_IN = 351 MHz		87
		f_IN = 451 MHz		87
		f_IN = 651 MHz		90
		f_IN = 751 MHz		87
		f_IN = 999 MHz		80
THD	Total harmonic distortion	f_IN = 30 MHz		86		dBc
		f_IN = 70 MHz		83
		f_IN = 130 MHz		78
		f_IN = 230 MHz		77
		f_IN = 351 MHz		75
		f_IN = 451 MHz		68
		f_IN = 651 MHz		60
		f_IN = 751 MHz		55
		f_IN = 999 MHz		45
SINAD	Signal-to-noise and distortion	f_IN = 30 MHz		69.2		dBc
		f_IN = 70 MHz	67	68.9
		f_IN = 130 MHz		68.5
		f_IN = 230 MHz	65.5	68.2
		f_IN = 351 MHz		67.3
		f_IN = 451 MHz		64.8
		f_IN = 651 MHz		58.5
		f_IN = 751 MHz		54
		f_IN = 999 MHz		45.4
	Two-tone SFDR	f_IN1 = 69 MHz, f_IN2 = 70 MHz, each tone at –7 dBFS		93		dBFS
		f_IN1 = 69 MHz, f_IN2 = 70 MHz, each tone at –16 dBFS		95
		f_IN1 = 297.5 MHz, f_IN2 = 302.5 MHz, each tone at –7 dBFS		85
		f_IN1 = 297.5 MHz, f_IN2 = 302.5 MHz, each tone at –16 dBFS		83
ENOB	Effective number of bits	f_IN = 70 MHz	10.8	11.2		Bits
ENOB	Effective number of bits	f_IN = 230 MHz	10.6	10.9		Bits
	RMS idle-channel noise	Inputs tied to common-mode		1.8		LSB
DIGITAL OUTPUTS
V_OD	Differential output voltage (±)		247	350	454	mV
V_OC	Common-mode output voltage		1.125		1.375	V
DIGITAL INPUTS
V_IH	High level input voltage	PWD (pin 33)	2			V
V_IL	Low level input voltage	PWD (pin 33)			0.8	V
I_IH	High level input current	PWD (pin 33)			1	μA
I_IL	Low level input current	PWD (pin 33)	–1			μA
	Input capacitance	PWD (pin 33)		2		pF

6.6 Timing Characteristics

Typical values at T_A = 25°C: minimum and maximum values over full temperature range T_MIN = –40°C to T_MAX = 85°C, sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-V_PP differential clock, unless otherwise noted.⁽¹⁾

		TEST CONDITIONS	MIN	NOM	MAX	UNIT
t_a	Aperture delay			200		ps
	Aperture jitter, rms	Internal jitter of the ADC		103		fs
	Latency			3.5		cycles
t_CLK	Clock period		2.5		50	ns
t_CLKH	Clock pulse duration, high		1			ns
t_CLKL	Clock pulse duration, low		1			ns
t_DRY	CLK to DRY delay⁽²⁾	Zero crossing, 10-pF parasitic loading to GND on each output pin	1000	1400	1800	ps
t_DATA	CLK to DATA/OVR delay⁽²⁾	Zero crossing, 10-pF parasitic loading to GND on each output pin	800	1400	2000	ps
t_SKEW	DATA to DRY skew	t_DATA – t_DRY, 10-pF parasitic loading to GND on each output pin	–500	0	500	ps
t_RISE	DRY/DATA/OVR rise time	10-pF parasitic loading to GND on each output pin		500		ps
t_FALL	DRY/DATA/OVR fall time	10-pF parasitic loading to GND on each output pin		500		ps

(1) Timing parameters are ensured by design or characterization, but not production tested.

(2) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to t_DATA to determine the overall propagation delay.

6.7 Typical Characteristics

At T_A = 25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-V_PP differential sinusoidal clock, analog input amplitude = –1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.