JAJSH87D April 2015 – April 2019 ADS54J60
PRODUCTION DATA.
The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after only 18 clock cycles + tPD (tPD of the gates and buffers is approximately 4 ns), thus enabling a quicker reaction to an overrange event.
The input voltage level at which the overload is detected is referred to as the threshold. The threshold is programmable using the FOVR THRESHOLD bits, as shown in Figure 68. The FOVR is triggered 18 clock cycles + tPD (tPD of the gates and buffers is approximately 4 ns) after the overload condition occurs.
The input voltage level at which the fast OVR is triggered is defined by Equation 2:
The default threshold is E3h (227d), corresponding to a threshold of –1 dBFS.
In terms of full-scale input, the fast OVR threshold can be calculated as Equation 3: