JAJSH87D April 2015 – April 2019 ADS54J60
PRODUCTION DATA.
This section provides three different example register writes. Table 16 describes a global power-down register write, Table 17 describes the register writes when the default lane setting (eight active lanes per device) is changed to four active lanes (LMFS = 4211), and Table 18 describes the register writes for 2X decimation with four active lanes (LMFS = 4222).
ADDRESS (Hex) | DATA (Hex) | COMMENT |
---|---|---|
0-011h | 80h | Set the master page |
0-026h | C0h | Set the global power-down |
ADDRESS (Hex) | DATA (Hex) | COMMENT |
---|---|---|
4-004h | 69h | Select the JESD digital page |
4-003h | 00h | Select the JESD digital page |
6-001h | 02h | Select the digital to 40X mode |
4-004h | 6Ah | Select the JESD analog page |
6-016h | 02h | Set the SERDES PLL to 40X mode |
ADDRESS (Hex) | DATA (Hex) | COMMENT |
---|---|---|
4-004h | 68h | Select the main digital page (6800h) |
4-003h | 00h | Select the main digital page (6800h) |
6-041h | 12h | Set decimate-by-2 (low-pass filter) |
6-04Dh | 08h | Enable decimation filter control |
6-072h | 08h | BUS_REORDER EN2 |
6-052h | 80h | BUS_REORDER EN1 |
6-000h | 01h | Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect). |
6-000h | 00h | |
4-004h | 69h | Select the JESD digital page (6900h) |
4-003h | 00h | Select the JESD digital page (6900h) |
6-031h | 0Ah | Output bus reorder for channel A |
6-032h | 0Ah | Output bus reorder for channel B |
6-001h | 31h | Program the JESD MODE and JESD FILTER register bits for LMFS = 4222. |
Table 19 lists the access codes for the ADS54J60 registers.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R/W | R-W | Read or write |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |