JAJSH87D April 2015 – April 2019 ADS54J60
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYNC REG | SYNC REG EN | JESD FILTER | JESD MODE | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-01h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SYNC REG | R/W | 0h | Register control for sync request.
0 = Normal operation 1 = ADC output data are replaced with K28.5 characters. Register bit SYNC REG EN must also be set to 1. |
6 | SYNC REG EN | R/W | 0h | Enables register control for sync request.
0 = Use the SYNC pin for sync requests 1 = Use the SYNC REG register bit for sync requests |
5-3 | JESD FILTER | R/W | 0h | These bits and the JESD MODE bits set the correct LMFS configuration for the JESD interface. The JESD FILTER setting must match the configuration in the decimation filter page.
000 = Filter bypass mode See Table 54 for valid combinations for register bits JESD FILTER along with JESD MODE. |
2-0 | JESD MODE | R/W | 01h | These bits select the number of serial JESD output lanes per ADC. The JESD PLL MODE register bit located in the JESD analog page must also be set accordingly.
001 = Default after reset(Eight active lanes) See Table 54 for valid combinations for register bits JESD FILTER along with JESD MODE. |
REGISTER BIT JESD FILTER | REGISTER BIT JESD MODE | DECIMATION FACTOR | NUMBER OF ACTIVE LANES PER DEVICE |
---|---|---|---|
000 | 100 | No decimation | Four lanes are active |
000 | 010 | No decimation | Four lanes are active |
000 | 001 | No decimation
(default after reset) |
Eight lanes are active |
111 | 001 | 4X (IQ) | Four lanes are active |
110 | 001 | 2X | Four lanes are active |
110 | 010 | 2X | Two lanes are active |
100 | 001 | 4X | Two lanes are active |
111 | 010 | 4X (IQ) | Two lanes are active |
100 | 010 | 4X | One lane is active |