JAJSDZ9 October 2017 ADS54J64
PRODUCTION DATA.
The initial lane alignment process is started by the receiving device by deasserting the SYNCb signal. When a logic low is detected on the SYNC input pins, as shown in Figure 67, the ADS54J64 starts transmitting comma (K28.5) characters to establish code group synchronization.
When synchronization is complete, the receiving device reasserts the SYNCb signal and the ADS54J64 starts the initial lane alignment sequence with the next local multi-frame clock boundary. The ADS54J64 transmits four multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end symbols and the second multi-frame also contains the JESD204 link configuration data.