JAJSDZ9 October 2017 ADS54J64
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYNC_REQ | OPT_SYNC_REQ | SYNCB_SEL_AB_CD | 0 | 0 | 0 | SERDES_MODE | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SYNC_REQ | R/W | 0h | This bit controls the SYNC register (bit 6 must be enabled). 0 : Normal operation 1 : ADC output data are replaced with K28.5 characters |
6 | OPT_SYNC_REQ | R/W | 0h | This bit enables SYNC operation. 0 : Normal operation 1 : Enables SYNC from the SYNC_REQ register bit |
5 | SYNCB_SEL_AB_CD | R/W | 0h | This bit selects which SYNCb input controls the JESD interface. 0 : Use the SYNCbAB, SYNCbCD pins 1 : When set in the SerDes AB SPI, SYNCbCD is used for the SerDes AB and CD; when set in the SerDes CD SPI, SYNCbAB is used for the SerDes AB and CD |
4-2 | 0 | R/W | 0h | Must read or write 0 |
1-0 | SerDes_MODE | R/W | 0h | These bits set the JESD output parameters. The CTRL_SER_MODE bit (register 20h, bit 6) must also be set to control these bits. These bits are auto configured for modes 0, 1, 3, and 7, but must be configured for modes 2, 4, and 6. |