JAJSPK6B December 2015 – January 2023 ADS54J66
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST PATTERN ON CHANNEL | 0 | 0 | 0 | 0 | |||
R/W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | TEST PATTERN ON CHANNEL | R/W | 0h | Test pattern output on channel A and B 0000 = Normal operation using ADC output data 0001 = Outputs all 0s 0010 = Outputs all 1s 0011 = Outputs toggle pattern: Output data are an alternating sequence of 101010101010 and 010101010101 0100 = Output digital ramp: output data increment by one LSB every clock cycle from code 0 to 16384 0110 = Single pattern: output data are custom pattern 1 (75h and 76h) 0111 = Double pattern: output data alternate between custom pattern 1 and custom pattern 2 1000 = Deskew pattern: output data are 2AAAh 1001 = SYNC pattern: output data are 7FFFh See the Section 8.1.6 section for more details. To use the test patterns, the interleave engine must be in bypass and the DC correction disabled (page 6100h addresses 0x18 and 0x68) and the ADC must be in bypass mode. |
3-0 | 0 | W | 0h | Must write 0. |