JAJSPK6B December 2015 – January 2023 ADS54J66
PRODUCTION DATA
The ADS54J66 can be configured using a serial programming interface, as described in this section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes. The ADS54J66 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Section 7.6.1 section) to access all register bits. Figure 7-19 shows timing diagram for serial interface signals. SPI registers are grouped in two banks with each bank containing different pages (see Figure 7-34).
First 4 MSBs of 16-bit address are special bits carrying information about register bank, page and channel to be programmed. Table 7-11 lists the purpose of each special bit.
SPI BITS | DESCRIPTION | OPTIONS |
---|---|---|
R/W | Read/write bit | 0 = SPI write 1 = SPI read back |
M | SPI bank access | 0 = Analog SPI bank (master and ADC page) 1 = Digital SPI bank (main digital, analog JESD, and digital JESD pages) |
P | JESD page selection bit | 0 = Page access 1 = Register access |
CH | SPI access for a specific channel of the digital SPI bank | 0 = Channel AB 1 = Channel CD By default, both channels are being addressed. |
ADDR [11:0] | SPI address bits | — |
DATA [7:0] | SPI data bits | — |