The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.
The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS54J69 | VQFNP (72) | 10.00 mm × 10.00 mm |
Changes from B Revision (February 2016) to C Revision
Changes from A Revision (January 2016) to B Revision
Changes from * Revision (May 2015) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLOCK, SYSREF | |||
CLKINM | 28 | I | Negative differential clock input for the ADC |
CLKINP | 27 | I | Positive differential clock input for the ADC |
SYSREFM | 34 | I | Negative external SYSREF input |
SYSREFP | 33 | I | Positive external SYSREF input |
CONTROL, SERIAL INTERFACE | |||
PDN | 50 | I/O | Power-down. Can be configured via an SPI register setting. Can be configured to fast overrange output for channel A via the SPI. |
RESET | 48 | I | Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor. |
SCLK | 6 | I | Serial interface clock input |
SDIN | 5 | I | Serial interface data input |
SDOUT | 11 | O | Serial interface data output. Can be configured to fast overrange output for channel B via the SPI. |
SEN | 7 | I | Serial interface enable |
DATA INTERFACE | |||
DA0M | 62 | O | JESD204B serial data negative outputs for channel A |
DA1M | 59 | ||
DA2M | 56 | ||
DA3M | 54 | ||
DA0P | 61 | O | JESD204B serial data positive outputs for channel A |
DA1P | 58 | ||
DA2P | 55 | ||
DA3P | 53 | ||
DB0M | 65 | O | JESD204B serial data negative outputs for channel B |
DB1M | 68 | ||
DB2M | 71 | ||
DB3M | 1 | ||
DB0P | 66 | O | JESD204B serial data positive outputs for channel B |
DB1P | 69 | ||
DB2P | 72 | ||
DB3P | 2 | ||
SYNC | 63 | I | Synchronization input for JESD204B port |
INPUT, COMMON MODE | |||
INAM | 41 | I | Differential analog negative input for channel A |
INAP | 42 | I | Differential analog positive input for channel A |
INBM | 14 | I | Differential analog negative input for channel B |
INBP | 13 | I | Differential analog positive input for channel B |
VCM | 22 | O | Common-mode voltage, 2.1 V. Note that analog inputs are internally biased to this pin through 600 Ω (effective), no external connection from the VCM pin to the INxP or INxM pin is required. |
POWER SUPPLY | |||
AGND | 18, 23, 26, 29, 32, 36, 37 | I | Analog ground |
AVDD | 9, 12, 15, 17, 25, 30, 35, 38, 40, 43, 44, 46 | I | Analog 1.9-V power supply |
AVDD3V | 10, 16, 24, 31, 39, 45 | I | Analog 3.0-V power supply for the analog buffer |
DGND | 3, 52, 60, 67 | I | Digital ground |
DVDD | 8, 47 | I | Digital 1.9-V power supply |
IOVDD | 4, 51, 57, 64, 70 | I | Digital 1.15-V power supply for the JESD204B transmitter |
NC, RES | |||
NC | 19, 20, 21 | — | Unused pins, do not connect |
RES | 49 | I | Reserved pin. Connect to DGND. |