9.1.1 Start-Up Sequence

The steps described in Table 60 are the recommended power-up sequence with the ADS54J69 in 20X or 40X mode.

9.1.2 Hardware Reset

Figure 129 and Table 61 show the timing for a hardware reset.

Figure 129. Hardware Reset Timing Diagram

9.1.3 SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is 98 dB for a 16-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for higher input frequencies. The decimation-by-2 process gives approximately an additional 3-dB improvement in SNR.

Equation 4.

The SNR limitation resulting from the sample clock jitter can be calculated by Equation 5:

Equation 5.

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (145 f_S) is set by the noise of the clock input buffer and the external clock jitter. T_Jitter can be calculated by Equation 6:

Equation 6.

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.

The ADS54J69 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 f_S. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 130.

Figure 130. SNR versus Input Frequency and External Clock Jitter

Half-band decimation filtering employed by the ADS54J69 reduces the affect of all contributors to SNR by 3 dB. Filtering makes the SNR curve in Figure 130 start at 74 dBFS despite a thermal noise of 71.1 dBFS.

Decimation filtering also improves the affect of jitter noise by 3 dB, and is equivalent to having 102 f_S as the effective aperture jitter instead of 120 f_S.

9.2.1 Design Requirements

9.2.1.1 Transformer-Coupled Circuits

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 300 MHz to achieve good phase and amplitude balances at the ADC inputs. When designing dc driving circuits, the ADC input impedance must be considered. Figure 132 and Figure 133 show the impedance (Z_IN = R_IN || C_IN) across the ADC input pins.

Figure 132. R_IN vs Input Frequency

Figure 133. C_IN vs Input Frequency

By using the simple drive circuit of Figure 134, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

Figure 134. Input Drive Circuit

9.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 134.

9.2.3 Application Curves

Figure 135 and Figure 136 show the typical performance at 170 MHz and 230 MHz, respectively.

SNR = 73 dBFS; SFDR = 93 dBc; SINAD = 73.18 dBFS; THD = 89 dBc; HD2 = 93 dBc; HD3 = 103 dBc; IL spur = 99 dBc; non HD2, HD3 spur = 94 dBc

Figure 135. FFT for 170-MHz Input Signal

SNR = 71.6 dBFS; SFDR = 80 dBc; SINAD = 71 dBFS; THD = 79 dBc; HD2 = –80 dBc; HD3 = –96 dBc; IL spur = 85 dBc; non HD2, HD3 spur = 92 dBc

Figure 136. FFT for 310-MHz Input Signal