SLWS207B May   2008  – January 2016 ADS5560 , ADS5562

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Electrical Characteristics for ADS5560 Fs = 40 MSPS
    7. 6.7  AC Electrical Characteristics for ADS5562, Fs = 80 MSPS
    8. 6.8  Electrical Characteristics for ADS5562
    9. 6.9  Electrical Characteristics for ADS5560
    10. 6.10 Digital Characteristics
    11. 6.11 Timing Characteristics for LVDS and CMOS Modes
    12. 6.12 Serial Interface Timing Characteristics
    13. 6.13 Reset Timing
    14. 6.14 Timing Characteristics at Lower Sampling Frequencies
    15. 6.15 Typical Characteristics
      1. 6.15.1 ADS5562 - 80 MSPS
      2. 6.15.2 ADS5560 - 40 MSPS
      3. 6.15.3 Valid Up to Max Clock Rate (ADS5562 or ADS5560)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Frequency Noise Suppression
      2. 7.3.2 Analog Input Circuit
        1. 7.3.2.1 Drive Circuit Recommendations
        2. 7.3.2.2 Example Driving Circuit
        3. 7.3.2.3 Input Common-Mode
        4. 7.3.2.4 Programmable Fine Gain
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Sampling Frequency Operation
      2. 7.4.2 Clock Input
        1. 7.4.2.1 Power-Down
          1. 7.4.2.1.1 Global STANDBY
          2. 7.4.2.1.2 Output Buffer Disable
          3. 7.4.2.1.3 Input Clock Stop
        2. 7.4.2.2 Power Supply Sequence
      3. 7.4.3 Output Interface
        1. 7.4.3.1 DDR LVDS Outputs
        2. 7.4.3.2 LVDS Buffer Current Programmability
        3. 7.4.3.3 LVDS Buffer Internal Termination
        4. 7.4.3.4 Parallel CMOS
        5. 7.4.3.5 Output Clock Position Programmability
      4. 7.4.4 Output Data Format
      5. 7.4.5 Reference
        1. 7.4.5.1 Internal Reference
        2. 7.4.5.2 External Reference
    5. 7.5 Programming
      1. 7.5.1 Device Programming Modes
      2. 7.5.2 Using Parallel Interface Control Only
        1. 7.5.2.1 Using Serial Interface Programming Only
        2. 7.5.2.2 Using Both Serial Interface And Parallel Controls
        3. 7.5.2.3 Description of Parallel Pins
      3. 7.5.3 Serial Interface
      4. 7.5.4 Register Initialization
    6. 7.6 Register Maps
      1. 7.6.1 Register Description
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADC5562
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Supply Decoupling
      2. 10.1.2 Exposed Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Power Supply Recommendations

The device requires a 3.3-V nominal supply for AVDD. The device also requires a 3.3-V supply for DRVDD. There are no specific sequence power-supply requirements during device power-up. AVDD, and DRVDD can power up in any order. It is recommended that the analog supply be low noise, such as would be the case if each analog supply was generated by its own linear regulator. The digital supply would be much more tolerant of supply noise and a DC-DC switching supply could be suitable for DRVDD.

At each power-supply pin, a 0.1-μF decoupling capacitor should be kept close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-μF, 1-μF, and 0.1-μF capacitors can be kept close to the supply source.