8.5.105 GPO0_TRIG_EVENT_SEL Register (Address = 0xC3) [reset = 0x2]
GPO0_TRIG_EVENT_SEL is shown in Figure 124 and described in Table 115.
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Figure 124. GPO0_TRIG_EVENT_SEL Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
GPO0_TRIG_EVENT_SEL[7:0] |
R/W-10b |
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Table 115. GPO0_TRIG_EVENT_SEL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-0 |
GPO0_TRIG_EVENT_SEL[7:0] |
R/W |
10b |
Select the inputs AIN/GPIO[7:0] which can trigger an event based update on GPO0.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO0 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit trigger GPO0 output.
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