8.5.112 GPO7_TRIG_EVENT_SEL Register (Address = 0xD1) [reset = 0x40]
GPO7_TRIG_EVENT_SEL is shown in Figure 131 and described in Table 122.
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Figure 131. GPO7_TRIG_EVENT_SEL Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
GPO7_TRIG_EVENT_SEL[7:0] |
R/W-1000000b |
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Table 122. GPO7_TRIG_EVENT_SEL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-0 |
GPO7_TRIG_EVENT_SEL[7:0] |
R/W |
1000000b |
Select the inputs AIN/GPIO[7:0] which can trigger an Event based update on GPO7.
0b = Alert flags for the AIN/GPIO corresponding to this bit do not trigger GPO7 output.
1b = Alert flags for the AIN/GPIO corresponding to this bit trigger GPO7 output.
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