JAJSHK8 June 2019 ADS7028
ADVANCE INFORMATION for pre-production products; subject to change without notice.
The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK speeds and still achieve full throughput. As described in Table 6, the host controller can use any of the four SPI-compatible protocols (SPI-00, SPI-01, SPI-10, or SPI-11) to access the device.
PROTOCOL | SCLK POLARITY
(At the CS Falling Edge) |
SCLK PHASE
(Capture Edge) |
CPOL_CPHA[1:0] | DIAGRAM |
---|---|---|---|---|
SPI-00 | Low | Rising | 00b | Figure 11 |
SPI-01 | Low | Falling | 01b | Figure 12 |
SPI-10 | High | Falling | 10b | Figure 11 |
SPI-11 | High | Rising | 11b | Figure 12 |
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00 protocol for data read and data write operations. To select a different SPI-compatible protocol, program the CPOL_CPHA[1:0] field. This first write operation must adhere to the SPI-00 protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol.