SBAS608C June   2014  – December 2015 ADS7042

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Companion Products
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Digital Voltage Levels
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Reference
      2. 10.3.2 Analog Input
      3. 10.3.3 ADC Transfer Function
      4. 10.3.4 Serial Interface
    4. 10.4 Device Functional Modes
      1. 10.4.1 Offset Calibration
        1. 10.4.1.1 Offset Calibration on Power-Up
        2. 10.4.1.2 Offset Calibration During Normal Operation
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Single-Supply DAQ with the ADS7042
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 Antialiasing Filter
          2. 11.2.1.2.2 Input Amplifier Selection
          3. 11.2.1.2.3 Reference Circuit
        3. 11.2.1.3 Application Curve
      2. 11.2.2 DAQ Circuit with the ADS7042 for Maximum SINAD
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
      3. 11.2.3 12-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements
        1. 11.2.3.1 Design Requirements
        2. 11.2.3.2 Detailed Design Procedure
        3. 11.2.3.3 Application Curve
  12. 12Power-Supply Recommendations
    1. 12.1 AVDD and DVDD Supply Recommendations
    2. 12.2 Estimating Digital Power Consumption
    3. 12.3 Optimizing Power Consumed by the Device
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DCU|8
  • RUG|8
サーマルパッド・メカニカル・データ
発注情報

8 Specifications

8.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
AVDD to GND –0.3 3.9 V
DVDD to GND –0.3 3.9 V
AINP to GND –0.3 AVDD + 0.3 V
AINM to GND –0.3 0.3 V
Digital input voltage to GND –0.3 DVDD + 0.3 V
Storage temperature, Tstg –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
AVDD Analog supply voltage range 1.65 3.6 V
DVDD Digital supply voltage range 1.65 3.6 V
TA Operating free-air temperature –40 125 °C

8.4 Thermal Information

THERMAL METRIC(1) ADS7042 UNIT
RUG (X2QFN) DCU (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 177.5 235.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.5 79.8 °C/W
RθJB Junction-to-board thermal resistance 76.7 117.6 °C/W
ψJT Junction-to-top characterization parameter 1.0 8.9 °C/W
ψJB Junction-to-board characterization parameter 76.7 116.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

At TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 1 MSPS, and VAINM = 0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span(1) 0 AVDD V
Absolute input voltage range AINP to GND –0.1 AVDD + 0.1 V
AINM to GND –0.1 0.1
CS Sampling capacitance 15 pF
SYSTEM PERFORMANCE
Resolution 12 Bits
NMC No missing codes 12 Bits
INL Integral nonlinearity AVDD = 3 V –1 ±0.7 1 LSB(2)
AVDD = 1.8 V –2 ±1 2
DNL Differential nonlinearity AVDD = 3 V –0.99 ±0.5 1 LSB
AVDD = 1.8 V –0.99 ±0.7 2
EO Offset error Uncalibrated AVDD = 1.65 V to 3.6 V ±12 LSB
Calibrated(6) AVDD = 3 V –3 ±0.5 3
AVDD = 1.8 V –4 ±1 4
dVOS/dT Offset error drift with temperature 5 ppm/°C
EG Gain error AVDD = 3 V –0.1 ±0.05 0.1 %FS
AVDD = 1.8 V –0.2 ±0.1 0.2
Gain error drift with temperature 2 ppm/°C
SAMPLING DYNAMICS
tACQ Acquisition time 200 ns
Maximum throughput rate 16-MHz SCLK, AVDD = 1.65 V to 3.6 V 1 MHz
DYNAMIC CHARACTERISTICS
SNR Signal-to-noise ratio(4) fIN = 2 kHz, AVDD = 3 V 69 70 dB
fIN = 2 kHz, AVDD = 1.8 V 68
THD Total harmonic distortion(4)(3) fIN = 2 kHz, AVDD = 3 V –80 dB
SINAD Signal-to-noise and distortion(4) fIN = 2 kHz, AVDD = 3 V 68 69.5 dB
fIN = 2 kHz, AVDD = 1.8 V 67.5
SFDR Spurious-free dynamic range(4) fIN = 2 kHz, AVDD = 3 V 80 dB
BW(fp) Full-power bandwidth At –3 dB, AVDD = 3 V 25 MHz
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH High-level input voltage(5) 0.65 DVDD DVDD + 0.3 V
VIL Low-level input voltage(5) –0.3 0.35 DVDD V
VOH High-level output voltage(5) At Isource = 500 µA 0.8 DVDD DVDD V
At Isource = 2 mA DVDD – 0.45 DVDD
VOL Low-level output voltage(5) At Isink = 500 µA 0 0.2 DVDD V
At Isink = 2 mA 0 0.45
POWER-SUPPLY REQUIREMENTS
AVDD Analog supply voltage 1.65 3 3.6 V
DVDD Digital I/O supply voltage 1.65 3 3.6 V
IAVDD Analog supply current At 1 MSPS with AVDD = 3 V 230 µA
At 100 kSPS with AVDD = 3 V 23
At 1 MSPS with AVDD = 1.8 V 130
PD Power dissipation At 1 MSPS with AVDD = 3 V 690 µW
At 100 kSPS with AVDD = 3 V 69
At 1 MSPS with AVDD = 1.8 V 234
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Calculated on the first nine harmonics of the input frequency.
(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified..
(5) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. See the Digital Voltage Levels section for more details.
(6) Refer to the Offset Calibration section for more details.

8.6 Timing Characteristics

All specifications are at TA = –40°C to 125°C, AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF, unless otherwise specified.
MIN TYP MAX UNIT
TIMING SPECIFICATIONS
fTHROUGHPUT Throughput 1 MSPS
tCYCLE Cycle time 1 µs
tCONV Conversion time 12.5 × tSCLK + tSU_CSCK ns
tDV_CSDO Delay time: CS falling to data enable 10 ns
tD_CKDO Delay time: SCLK falling to (next) data valid on DOUT, AVDD = 1.8 V to 3.6 V 30 ns
Delay time: SCLK falling to (next) data valid on DOUT, AVDD = 1.65 V to 1.8 V 50 ns
tDZ_CSDO Delay time: CS rising to DOUT going to 3-state 5 ns
TIMING REQUIREMENTS
tACQ Acquisition time 200 ns
fSCLK SCLK frequency 0.016 16 MHz
tSCLK SCLK period 62.5 ns
tPH_CK SCLK high time 0.45 0.55 tSCLK
tPL_CK SCLK low time 0.45 0.55 tSCLK
tPH_CS CS high time 60 ns
tSU_CSCK Setup time: CS falling to SCLK falling 15 ns
tD_CKCS Delay time: last SCLK falling to CS rising 10 ns
ADS7042 tim_spi_bas608_B.gif Figure 1. Timing Diagram

8.7 Typical Characteristics

At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
ADS7042 C001_SBAS608.png
SNR = 70.62 dB THD = –83.96 dB fIN = 2 kHz
Number of samples = 32768
Figure 2. Typical FFT
ADS7042 C003_SBAS608.png
fIN = 2 kHz
Figure 4. SNR and SINAD vs Temperature
ADS7042 C005_SBAS608.png
Figure 6. SNR and SINAD vs Reference Voltage (AVDD)
ADS7042 C008_SBAS608.png
Figure 8. THD vs Input Frequency
ADS7042 C007_SBAS608.png
Figure 10. SFDR vs Free-Air Temperature
ADS7042 C011_SBAS608.png
Figure 12. SFDR vs Reference Voltage (AVDD)
ADS7042 C013_SBAS608.png
Figure 14. Offset vs Free-Air Temperature
ADS7042 C015_SBAS608.png
Figure 16. Gain Error vs Free-Air Temperature
ADS7042 C017_SBAS608.png
AVDD = 3 V
Figure 18. Typical DNL
ADS7042 C019_SBAS608.png
AVDD = 1.8 V
Figure 20. Typical DNL
ADS7042 C021_SBAS608.png
Figure 22. DNL vs Free-Air-Temperature
ADS7042 C023_SBAS608.png
Figure 24. INL vs Free-Air-Temperature
ADS7042 C025_SBAS608.png
fSample = 1 MSPS
Figure 26. AVDD Supply Current vs Free-Air Temperature
ADS7042 C027_SBAS608.png
Figure 28. AVDD Supply Current vs AVDD Voltage
ADS7042 C002_SBAS608.png
SNR = 70.22 dB THD = –81.58 dB fIN = 250 kHz
Number of samples = 32768
Figure 3. Typical FFT
ADS7042 C004_SBAS608.png
Figure 5. SNR and SINAD vs Input Frequency
ADS7042 C006_SBAS608.png
Figure 7. THD vs Free-Air Temperature
ADS7042 C010_SBAS608.png
Figure 9. THD vs Reference Voltage (AVDD)
ADS7042 C009_SBAS608.png
Figure 11. SFDR vs Input Frequency
ADS7042 C012_SBAS608.png
Mean code = 2048.04 Sigma = 0.27
Figure 13. DC Input Histogram
ADS7042 C014_SBAS608.png
Figure 15. Offset vs Reference Voltage (AVDD)
ADS7042 C016_SBAS608.png
Figure 17. Gain Error vs Reference Voltage (AVDD)
ADS7042 C018_SBAS608.png
AVDD = 3 V
Figure 19. Typical INL
ADS7042 C020_SBAS608.png
AVDD = 1.8 V
Figure 21. Typical INL
ADS7042 C022_SBAS608.png
Figure 23. DNL vs Reference Voltage (AVDD)
ADS7042 C024_SBAS608.png
Figure 25. INL vs Reference Voltage (AVDD)
ADS7042 C026_SBAS608.png
Figure 27. AVDD Supply Current vs Throughput
ADS7042 C028_SBAS608.png
Figure 29. AVDD Static Current vs Free-Air Temperature