JAJSE72 December   2017 ADS7047

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Product Family
      2. 8.3.2 Analog Input
      3. 8.3.3 Reference
      4. 8.3.4 ADC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 ACQ State
      2. 8.4.2 CNV State
      3. 8.4.3 OFFCAL State
        1. 8.4.3.1 Offset Calibration on Power-Up
        2. 8.4.3.2 Offset Calibration During Normal Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 2-Channel, Simultaneous Sampling Data Acquisition Using the ADS7047
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Low Distortion Charge Kickback Filter Design
          2. 9.2.1.2.2 Input Amplifier Selection
          3. 9.2.1.2.3 Reference Circuit
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Improving Precision of Single-Ended Signal Source Measurements Using the ADS7047
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Optimizing Power Consumed by the Device
      1. 10.2.1 Estimating Digital Power Consumption
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Power Supply Recommendations

10.1 AVDD and DVDD Supply Recommendations

The device has two separate power supplies: AVDD and DVDD.

AVDD powers the analog blocks and is also used as the reference voltage for the analog-to-digital conversion. Use a low-noise, low-dropout regulator (LDO) or a discrete reference to supply AVDD (see the Reference and Application Information sections). Always set the AVDD supply to be greater than or equal to the maximum input signal to avoid code saturation. Decouple the AVDD pin to the GND pin with a 3.3-µF ceramic decoupling capacitor.

DVDD is used for the interface circuits. Decouple the DVDD pin to the GND pin with a 1-µF ceramic decoupling capacitor. Figure 46 shows the decoupling recommendations.

ADS7047 ads7056-power-supply-decoupling-sbas769.gif Figure 46. Power-Supply Decoupling

10.2 Optimizing Power Consumed by the Device

In order to best optimize the power consumed by the device, use the following design considerations:

  • Keep the analog supply voltage (AVDD) in the specified operating range and equal to the maximum analog input voltage.
  • Keep the digital supply voltage (DVDD) in the specified operating range and at the lowest value supported by the host controller.
  • Reduce the load capacitance on the SDO output.
  • Run the device at the optimum throughput. Power consumption reduces proportionally with the throughput.

10.2.1 Estimating Digital Power Consumption

The current consumption from the DVDD supply depends on the DVDD voltage, the load capacitance on the SDO pin (CLOAD-SDO), and the output code, and can be calculated as:

Equation 2. IDVDD = CLOAD-SDO × V × f

where

  • CLOAD-SDO = Load capacitance on the SDO pin
  • V = DVDD supply voltage
  • f = Frequency of transitions on the SDO output

The number of transitions on the SDO output depends on the output code, and thus changes with the analog input. The maximum value of f occurs when data output on the SDO change on every SCLK (that is, for output codes of AAAh or 555h). With an output code of AAAh or 555h, f = 18 MHz and when CLOAD-SDO = 20 pF and DVDD = 1.8 V, IDVDD = 650 µA.