JAJSE73 December   2017 ADS7052

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Product Family
      2. 8.3.2 Analog Input
      3. 8.3.3 Reference
      4. 8.3.4 ADC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 ACQ State
      2. 8.4.2 CNV State
      3. 8.4.3 OFFCAL State
        1. 8.4.3.1 Offset Calibration on Power-Up
        2. 8.4.3.2 Offset Calibration During Normal Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Supply Data Acquisition With the ADS7052
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Low Distortion Charge Kickback Filter Design
          2. 9.2.1.2.2 Input Amplifier Selection
          3. 9.2.1.2.3 Reference Circuit
        3. 9.2.1.3 Application Curve
      2. 9.2.2 High Bandwidth (200 kHz) Data Acquisition With the ADS7052
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
      3. 9.2.3 14-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Optimizing Power Consumed by the Device
      1. 10.2.1 Estimating Digital Power Consumption
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The two primary supporting circuits required to maximize the performance of a high-precision, successive approximation register (SAR) analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing the input driver circuit, reference driver circuit, and provides typical application circuits designed for the device.

9.2 Typical Applications

9.2.1 Single-Supply Data Acquisition With the ADS7052

ADS7052 apps1_se_sbas769.gif Figure 40. DAQ Circuit: Single-Supply DAQ

9.2.1.1 Design Requirements

The goal of the circuit shown in Figure 40 is to design a single-supply data acquisition (DAQ) circuit based on the ADS7052 with SNR greater than 74 dB and THD less than –85 dB for input frequencies of 2 kHz at a throughput of 1 MSPS for applications such as low power data acquisition systems, sensor monitoring, and environmental sensing.

9.2.1.2 Detailed Design Procedure

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and charge kickback filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a high-precision ADC.

9.2.1.2.1 Low Distortion Charge Kickback Filter Design

Figure 41 shows the input circuit of a typical SAR ADC. During the acquisition phase, the SW switch closes and connects the sampling capacitor (CSH) to the input driver circuit. This action introduces a transient on the input pins of the SAR ADC. An ideal amplifier with 0 Ω of output impedance and infinite current drive can settle this transient in zero time. For a real amplifier with non-zero output impedance and finite drive strength, this switched capacitor load can create stability issues.

ADS7052 se_filter_sbas769.gif Figure 41. Input Sample-and-Hold Circuit for a Typical SAR ADC

For ac signals, the filter bandwidth must be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to 16 pF. Thus, the value of CFLT is greater than 320 pF. Select a COG- or NPO-type capacitor because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.

Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design.

9.2.1.2.2 Input Amplifier Selection

The input amplifier bandwidth is typically much higher than the cutoff frequency of the charge kickback filter. Thus, TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers can require more bandwidth than others to drive similar filters. To learn more about the SAR ADC input driver design, see the TI Precision Labs training video series.

For the application circuit of Figure 40, the OPA836 is selected for its high bandwidth (205 MHz), low noise (4.6 nV/√Hz), high output drive capacity (45 mA), and fast settling response (22 ns for 0.1% settling).

9.2.1.2.3 Reference Circuit

The ADS70xx uses the analog supply voltage (AVDD) as the reference voltage for the analog to digital conversion. During the conversion process, the internal capacitors are switched to the level of the AVDD pin as per the successive approximation algorithm. A voltage reference must be selected with low temperature drift, high output current drive and low output impedance. For this application, the REF1933 was selected as the voltage reference and analog power supply for the ADC. The REF1933 has excellent temperature drift performance (25 ppm/°C), good initial accuracy (0.1%), high output drive capability (25 mA), and low quiescent current (360 µA). The REF1933 also provides a bias voltage output of half the reference voltage (VREF/2) which can be used as the common mode input for the amplifier.

TI recommends a 3.3-µF (CAVDD), low equivalent series resistance (ESR) ceramic capacitor between the AVDD and GND pins. This decoupling capacitor provides the instantaneous charge required by the internal circuit during the conversion process and maintains a stable dc voltage on the AVDD pin.

9.2.1.3 Application Curve

Figure 42 provides the measurement result for the circuit described in Figure 40.

ADS7052 D001_SBAS858.gif
SNR = 75.3 dB, THD = –90.1 dB, SINAD = 75 dB
Figure 42. Test Results for the ADS7052 and OPA836 for a 2-kHz Input

9.2.2 High Bandwidth (200 kHz) Data Acquisition With the ADS7052

ADS7052 apps2_se_sbas769.gif Figure 43. High Bandwidth DAQ Circuit

9.2.2.1 Design Requirements

Applications such as motor control feedback loops, motor encoders, global positioning systems (GPS), and optical modules need analog-to-digital converters that are interfaced to high-frequency sensors (200 kHz to 1 MHz). The goal of the circuit described in Figure 43 is to design a circuit based on the ADS7052 with SNR greater than 73 dB and THD less than –85 dB for input frequencies of 200 kHz at a throughput of 1 MSPS.

9.2.2.2 Detailed Design Procedure

To achieve a SINAD greater than 73 dB and THD less than –85 dB, the operational amplifier must have high bandwidth in order to settle the input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 43, the THS4031 is selected for its high bandwidth (275 MHz), low total harmonic distortion of –90 dB at 1 MHz, and ultra-low noise of 1.6 nV/√Hz. The THS4031 is powered up from dual power supply (VDD = 6 V and VSS = –6 V).

For this application, the REF1933 was selected as the voltage reference and analog power supply for the ADC. The REF1933 has excellent temperature drift performance (25 ppm/°C), good initial accuracy (0.1%), high output drive capability (25 mA), and low quiescent current (360 µA). The REF1933 also provides a bias voltage output of half the reference voltage (VREF / 2) that can be used as the common-mode input for the amplifier.

The SNR performance at higher input frequency is highly dependant on jitter on the sampling signal (CS). TI recommends selecting a clock source that has very low jitter (< 20-ps RMS).

9.2.2.3 Application Curve

Figure 44 shows the FFT plot for the ADS7052 with a 200-kHz input frequency used for the circuit in Figure 43.

ADS7052 D003_SBAS858.gif
SNR = 74.2 dB, THD = –90.4 dB, SINAD = 74 dB
Figure 44. Test Results for the ADS7052 and THS4031 for a 200-kHz Input

9.2.3 14-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements

ADS7052 ads7056-interfacing-device-with-sensors-sbas769.gif Figure 45. Interfacing the Device Directly With Sensors

In applications where the input is very slow moving and the overall system ENOB is not a critical parameter, a DAQ circuit can be designed without the input driver for the ADC. This type of a use case is of particular interest for applications in which the primary goal is to achieve the absolute lowest power possible. Typical applications that fall into this category are low-power sensor applications (such as temperature, pressure, humidity, gas, and chemical).

9.2.3.1 Design Requirements

For this design example, use the parameters listed in Table 5 as the input parameters.

Table 5. Design Parameters

DESIGN PARAMETER GOAL VALUE
Throughput 10 kSPS
SNR at 100 Hz 74 dB
THD at 100 Hz –85 dB
SINAD at 100 Hz 73 dB
ENOB 12 bits
Power 20 µW

9.2.3.2 Detailed Design Procedure

The ADS7052 can be directly interfaced with sensors at lower throughput without the need of an amplifier buffer, however, the output impedance of the sensor must be taken into account. The sensor must be capable of driving the switched capacitor load of a SAR ADC and settling the analog input signal within the acquisition time of the SAR ADC. Figure 45 shows the simplified circuit for a sensor as a voltage source with output impedance (Rsource). As the output impedance of the sensor increases, the device requires more acquisition time to settle the input signal to the desired accuracy.

The acquisition time of a SAR ADC (such as the ADS7052 ) can be increased by reducing throughput in the following ways:

  1. Reducing the SCLK frequency to reduce the throughput or
  2. Keeping the SCLK fixed at the highest permissible value (that is, 24 MHz for the device) and increasing the CS high time

Table 6 lists the acquisition time for the above two cases for a throughput of 10 kSPS. Clearly, case 2 provides more acquisition time for the input signal to settle.

Table 6. Acquisition Time With Different SCLK Frequencies

CASE SCLK tcycle CONVERSION TIME
(= 18 × tSCLK)		 ACQUISITION TIME
(= tcycle – tconv)
1 0.24 MHz 100 µs 75 µs 25 µs
2 24 MHz 100 µs 0.75 µs 99.25 µs

9.2.3.3 Application Curve

Figure 46 provides the results for ENOB achieved from the ADS7052 for case 2 at different throughputs with different values of sensor output impedance.

ADS7052 D039_SBAS769_old.gif Figure 46. Effective Number of Bits (ENOB) Achieved From the ADS7052 at Different Throughputs

Table 7 shows the results and performance summary for this 14-bit, 10-kSPS DAQ circuit application with a sensor output impedance of 22 kΩ.

Table 7. Results and Performance Summary for a 14-Bit, 10-kSPS DAQ Circuit for DC Sensor Measurements

DESIGN PARAMETER GOAL VALUE ACHIEVED RESULT
Throughput 10 kSPS 10 kSPS
SNR at 100 Hz 74 dB 75 dB
THD at 100 Hz –85 dB –89 dB
SINAD at 100 Hz 73 dB 74.3 dB
ENOB 12 bits 12.05 bits
Power 20 µW 17 µW