JAJSE73 データシート

6.1 Absolute Maximum Ratings⁽¹⁾

	MIN	MAX	UNIT
AVDD to GND	–0.3	3.9	V
DVDD to GND	–0.3	3.9	V
AINP to GND	–0.3	AVDD + 0.3	V
AINM to GND	–0.3	0.3	V
Input current to any pin except supply pins	–10	10	mA
Digital input voltage to GND	–0.3	DVDD + 0.3	V
Storage temperature, T_stg	–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
AVDD	Analog supply voltage range	1.65	3.3	3.6	V
DVDD	Digital supply voltage range	1.65	1.8	3.6	V
T_A	Operating free-air temperature	–40	25	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS7052	UNIT
		RUG (X2QFN)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	177.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	51.5	°C/W
R_θJB	Junction-to-board thermal resistance	76.7	°C/W
ψ_JT	Junction-to-top characterization parameter	1	°C/W
ψ_JB	Junction-to-board characterization parameter	76.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at AVDD = 3.3 V, DVDD = 1.65 V to 3.6 V, f_sample = 1 MSPS, and V_AINM = 0 V (unless otherwise noted); minimum and maximum values for T_A = –40°C to +125°C; typical values at T_A = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
	Full-scale input voltage span⁽¹⁾		0		AVDD	V
	Absolute input voltage range	AINP to GND	–0.1		AVDD + 0.1	V
	Absolute input voltage range	AINM to GND	–0.1		0.1	V
C_S	Sampling capacitance			16		pF
SYSTEM PERFORMANCE
	Resolution			14		Bits
NMC	No missing codes		14			Bits
INL⁽⁸⁾	Integral nonlinearity		–3.75	±2	3.75	LSB⁽²⁾
DNL	Differential nonlinearity		–0.99	±0.5	1	LSB
E_O⁽⁸⁾	Offset error	After calibration⁽⁷⁾	–6	±1	6	LSB
dV_OS/dT	Offset error drift with temperature			1.75		ppm/°C
E_G⁽⁸⁾	Gain error		–0.1	±0.01	0.1	%FS
	Gain error drift with temperature			0.5		ppm/°C
SAMPLING DYNAMICS
t_CONV	Conversion time			18 × t_SCLK		ns
t_ACQ	Acquisition time		230			ns
f_SAMPLE	Maximum throughput rate	24-MHz SCLK, AVDD = 1.65 V to 3.6 V			1	MHz
	Aperture delay			3		ns
	Aperture jitter, RMS			12		ps
DYNAMIC CHARACTERISTICS
SNR	Signal-to-noise ratio⁽⁴⁾	AVDD = 3.3 V, f_IN = 2 kHz	71.5	74.9		dB
SNR	Signal-to-noise ratio⁽⁴⁾	AVDD = 2.5 V, f_IN = 2 kHz		73.7		dB
THD	Total harmonic distortion⁽⁴⁾⁽³⁾	f_IN = 2 kHz		–92		dB
		f_IN = 100 kHz		–90
		f_IN = 200 kHz		–87
SINAD	Signal-to-noise and distortion⁽⁴⁾	f_IN = 2 kHz	71.5	74.8		dB
		f_IN = 100 kHz		74.7
		f_IN = 200 kHz		74.5
SFDR	Spurious-free dynamic range⁽⁴⁾	f_IN = 2 kHz		89.8		dB
		f_IN = 100 kHz		91
		f_IN = 200 kHz		87
BW_(fp)	Full-power bandwidth	At –3 dB		200		MHz
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
V_IH	High-level input voltage⁽⁵⁾		0.65 DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage⁽⁵⁾		–0.3		0.35 DVDD	V
V_OH	High-level output voltage⁽⁵⁾	At I_source = 500 µA	0.8 DVDD		DVDD	V
V_OH	High-level output voltage⁽⁵⁾	At I_source = 2 mA	DVDD – 0.45		DVDD	V
V_OL	Low-level output voltage⁽⁵⁾	At I_sink = 500 µA	0		0.2 DVDD	V
V_OL	Low-level output voltage⁽⁵⁾	At I_sink = 2 mA	0		0.45	V
POWER-SUPPLY REQUIREMENTS
AVDD	Analog supply voltage		1.65	3	3.6	V
DVDD	Digital I/O supply voltage		1.65	3	3.6	V
I_AVDD	Analog supply current	AVDD = 3.3 V, f_SAMPLE = 1 MSPS		450	500	µA
		AVDD = 3.3 V, f_SAMPLE = 100 kSPS		46	50
		AVDD = 3.3 V, f_SAMPLE = 10 kSPS		5
		AVDD = 1.8 V, f_SAMPLE = 1 MSPS		230
		Static current with CS and SCLK high		0.02
I_DVDD	Digital supply current	DVDD = 1.8 V, CSDO = 20 pF, output code = 2AAAh⁽⁶⁾		250		µA
I_DVDD	Digital supply current	DVDD = 1.8 V, static current with CS and SCLK high		0.01		µA

(1) Ideal input span; does not include gain or offset error.

(2) LSB means least significant bit.

(3) Calculated on the first nine harmonics of the input frequency.

(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise noted.

(5) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Parameter Measurement Information section for details.

(6) See the Estimating Digital Power Consumption section for details.

(7) See the OFFCAL State section for details.

(8) See Figure 31, Figure 29, and Figure 30 for statistical distribution data for INL, offset error, and gain error.

6.6 Timing Requirements

all specifications are at AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and C_LOAD-SDO = 20 pF (unless otherwise noted); minimum and maximum values for T_A = –40°C to +125°C; typical values at T_A = 25°C

		MIN	MAX	UNIT
t_CLK	Time period of SCLK	41.66		ns
t_{su_CSCK}	Setup time: CS falling edge to SCLK falling edge	7		ns
t_{ht_CKCS}	Hold time: SCLK rising edge to CS rising edge	8		ns
t_{ph_CK}	SCLK high time	0.45	0.55	t_SCLK
t_{pl_CK}	SCLK low time	0.45	0.55	t_SCLK
t_{ph_CS}	CS high time	15		ns

6.7 Switching Characteristics

all specifications are at AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and C_LOAD-SDO = 20 pF (unless otherwise noted); minimum and maximum values for T_A = –40°C to +125°C; typical values at T_A = 25°C

PARAMETER		MIN	TYP	MAX	UNIT
t_CYCLE⁽¹⁾	Cycle time	1000			ns
t_CONV	Conversion time		18 × t_SCLK		ns
t_{den_CSDO}	Delay time: CS falling edge to data enable			6.5	ns
t_{d_CKDO}	Delay time: SCLK rising edge to (next) data valid on SDO			10	ns
t_{ht_CKDO}	SCLK rising edge to current data invalid	2.5			ns
t_{dz_CSDO}	Delay time: CS rising edge to SDO going to tri-state	5.5			ns