JAJSIN5C February   2020  – September 2023 ADS7066

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
      2. 7.3.2  Reference
        1. 7.3.2.1 External Reference
        2. 7.3.2.2 Internal Reference
      3. 7.3.3  ADC Transfer Function
      4. 7.3.4  ADC Offset Calibration
      5. 7.3.5  Programmable Averaging Filters
      6. 7.3.6  CRC on Data Interface
      7. 7.3.7  Oscillator and Timing Control
      8. 7.3.8  Diagnostic Modes
        1. 7.3.8.1 Bit-Walk Test Mode
        2. 7.3.8.2 Fixed Voltage Test Mode
      9. 7.3.9  Output Data Format
        1. 7.3.9.1 Status Flags
        2. 7.3.9.2 Output CRC (Device to Host)
        3. 7.3.9.3 Input CRC (Host to Device)
      10. 7.3.10 Device Programming
        1. 7.3.10.1 Enhanced-SPI Interface
        2. 7.3.10.2 Daisy-Chain Mode
        3. 7.3.10.3 Register Read/Write Operation
          1. 7.3.10.3.1 Register Write
          2. 7.3.10.3.2 Register Read
            1. 7.3.10.3.2.1 Register Read With CRC
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power-Up and Reset
      2. 7.4.2 Manual Mode
      3. 7.4.3 On-the-Fly Mode
      4. 7.4.4 Auto-Sequence Mode
    5. 7.5 ADS7066 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Charge-Kickback Filter and ADC Amplifier
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD and DVDD Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-6FBBA035-D837-4449-A521-88188C20FBCB-low.gif Figure 5-1 RTE Package,16-Pin WQFN(Top View)
Table 5-1 Pin Functions: RTE Package
PIN TYPE(1) DESCRIPTION
NAME RTE
AIN0/GPIO0 15 AI, DI, DO Channel 0; configurable as either an analog input (default) or general-purpose input/output (GPIO).
AIN1/GPIO1 16 AI, DI, DO Channel 1; configurable as either an analog input (default) or GPIO.
AIN2/GPIO2 1 AI, DI, DO Channel 2; configurable as either an analog input (default) or GPIO.
AIN3/GPIO3 2 AI, DI, DO Channel 3; configurable as either an analog input (default) or GPIO.
AIN4/GPIO4 3 AI, DI, DO Channel 4; configurable as either an analog input (default) or GPIO.
AIN5/GPIO5 4 AI, DI, DO Channel 5; configurable as either an analog input (default) or GPIO.
AIN6/GPIO6 5 AI, DI, DO Channel 6; configurable as either an analog input (default) or GPIO.
AIN7/GPIO7 6 AI, DI, DO Channel 7; configurable as either an analog input (default) or GPIO.
AVDD 7 P Analog supply voltage. Connect a 1-µF capacitor to GND.
CS 11 DI Chip-select input pin; active low.
The device takes control of the data bus when CS is low.
The SDO pin goes to Hi-Z when CS is high.
DVDD 10 P Digital I/O supply voltage. Connect a 1-µF capacitor to GND.
GND 9 P Ground for power supply, all analog and digital signals are referred to this pin.
REF 8 P Internal reference buffer output; external reference input. Connect a 1-µF capacitor to GND.
SCLK 13 DI Clock input pin for the SPI interface.
SDI 14 DI Serial data input pin for SPI interface.
SDO 12 DO Serial data output pin for SPI interface.
Thermal Pad Pad P Exposed thermal pad. Connect to ground.
(1) AI = analog input, DI = digital input, DO = digital output, P = power supply.
GUID-A08AB18F-0C47-4987-B7F9-2FE3C89151B8-low.svg Figure 5-2 YBH Package,16-Pin DSBGA
(Top View)
Table 5-2 Pin Functions: YBH Package
PIN TYPE(1) DESCRIPTION
YBH NAME
A1 AIN5/GPIO5 AI, DI, DO Channel 5; configurable as either an analog input (default) or GPIO.
A2 DVDD P Digital I/O supply voltage. Connect a 1-µF capacitor to GND.
A3 AVDD P Analog supply voltage. Connect a 1-µF capacitor to GND.
A4 REF P Internal reference buffer output; external reference input. Connect a 1-µF capacitor to GND.
B1 AIN4/GPIO4 AI, DI, DO Channel 4; configurable as either an analog input (default) or GPIO.
B2 AIN6/GPIO6 AI, DI, DO Channel 6; configurable as either an analog input (default) or GPIO.
B3 AIN7/GPIO7 AI, DI, DO Channel 7; configurable as either an analog input (default) or GPIO.
B4 GND P Ground for power supply, all analog and digital signals are referred to this pin.
C1 AIN3/GPIO3 AI, DI, DO Channel 3; configurable as either an analog input (default) or GPIO.
C2 AIN1/GPIO1 AI, DI, DO Channel 1; configurable as either an analog input (default) or GPIO.
C3 AIN0/GPIO0 AI, DI, DO Channel 0; configurable as either an analog input (default) or general-purpose input/output (GPIO).
C4 CS DI Chip-select input pin; active low.
The device takes control of the data bus when CS is low.
The SDO pin goes to Hi-Z when CS is high.
D1 AIN2/GPIO2 AI, DI, DO Channel 2; configurable as either an analog input (default) or GPIO.
D2 SDI DI Serial data input pin for SPI interface.
D3 SDO DO Serial data output pin for SPI interface.
D4 SCLK DI Clock input pin for the SPI interface.
(1) AI = analog input, DI = digital input, DO = digital output, P = power supply.