JAJSIN5C February   2020  – September 2023 ADS7066

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
      2. 7.3.2  Reference
        1. 7.3.2.1 External Reference
        2. 7.3.2.2 Internal Reference
      3. 7.3.3  ADC Transfer Function
      4. 7.3.4  ADC Offset Calibration
      5. 7.3.5  Programmable Averaging Filters
      6. 7.3.6  CRC on Data Interface
      7. 7.3.7  Oscillator and Timing Control
      8. 7.3.8  Diagnostic Modes
        1. 7.3.8.1 Bit-Walk Test Mode
        2. 7.3.8.2 Fixed Voltage Test Mode
      9. 7.3.9  Output Data Format
        1. 7.3.9.1 Status Flags
        2. 7.3.9.2 Output CRC (Device to Host)
        3. 7.3.9.3 Input CRC (Host to Device)
      10. 7.3.10 Device Programming
        1. 7.3.10.1 Enhanced-SPI Interface
        2. 7.3.10.2 Daisy-Chain Mode
        3. 7.3.10.3 Register Read/Write Operation
          1. 7.3.10.3.1 Register Write
          2. 7.3.10.3.2 Register Read
            1. 7.3.10.3.2.1 Register Read With CRC
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power-Up and Reset
      2. 7.4.2 Manual Mode
      3. 7.4.3 On-the-Fly Mode
      4. 7.4.4 Auto-Sequence Mode
    5. 7.5 ADS7066 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Charge-Kickback Filter and ADC Amplifier
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD and DVDD Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at AVDD = 3 V to 5.5 V, DVDD = 1.65 V to 5.5 V, VREF = 2.5 V (internal), and maximum throughput (unless otherwise noted); minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
CIN Input capacitance ADC and MUX capacitance 30 pF
DC PERFORMANCE
Resolution No missing codes 16 Bits
DNL Differential nonlinearity –0.75 ±0.4 0.75 LSB
INL Integral nonlinearity –4 ±1 4 LSB
V(OS) Input offset error Post offset calibration, OSR[2:0] = 7 –7 ±0.5 7 LSB
dVOS/dT Input offset thermal drift Post offset calibration, OSR[2:0] = 7 ±0.6 ppm/°C
Offset error match OSR[2:0] = 7 –2.75 0.5 2.75 LSB
GE Gain error(1) External VREF = 2.5 V, OSR[2:0] = 7 –0.05 ±0.01 0.05 %FSR
dGE/dT Gain error thermal drift External VREF = 2.5 V, OSR[2:0] = 7 ±0.5 ppm/°C
Gain error match
OSR[2:0] = 7

 –0.005 ±0.001 0.005 %FSR
AC PERFORMANCE
SINAD Signal-to-noise + distortion ratio fIN = 2 kHz, VREF = 2.5V (internal) 84.3 86.5 dB
fIN = 2 kHz, VREF = 5 V, AVDD = 5 V 88.75 91
SNR Signal-to-noise ratio fIN = 2 kHz, VREF = 2.5V (internal) 84.5 86.8 dB
fIN = 2 kHz, VREF = 5 V, AVDD = 5 V 90 91.9
THD Total harmonic distortion fIN = 2 kHz –100 dB
SFDR Spurious-free dynamic range fIN = 2 kHz 101 dB
Isolation crosstalk fIN = 10 kHz –110 dB
REFERENCE
VREF Internal reference output voltage(3) at TA= 25℃ 2.497 2.5 2.503 V
dVREF/dT Internal reference voltage temperature drift 6 19 ppm/°C
CREF Decoupling capacitor at REF pin 1 10 µF
DIGITAL INPUTS
VIL Input low logic level For CS, SCLK and SDI pins –0.3 0.3 DVDD V
For GPIOX (2) pins –0.3 0.3 AVDD
VIH Input high logic level For CS, SCLK and SDI pins 0.7 DVDD DVDD V
For GPIOX pins 0.7 AVDD AVDD
DIGITAL OUTPUTS
VOL Output low logic level For SDO pin, IOL = 500 µA sink 0 0.2 DVDD V
For GPIOX (2) pins, IOL = 500 µA sink 0 0.2 AVDD
VOH Output high logic level For SDO pin, IOH = 500 µA source 0.8 DVDD DVDD V
For GPIOX (2) pins, IOH = 500 µA source 0.8 AVDD AVDD
POWER SUPPLY
IAVDD Analog supply current AVDD = 3.3 V, external reference 0.7 0.91 mA
AVDD = 3.3 V, internal reference 1.2 1.56 mA
No conversion, external reference 250 µA
No conversion, internal reference 800 µA
(1) These specifications include full temperature range variation but not the error contribution from internal reference.
(2) GPIOX refers to GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, and GPIO7 pins.
(3) Does not include the variation in voltage resulting from solder shift effects.