8.6.4 OSR_CFG Register (Address = 0x3) [reset = 0x0]
OSR_CFG is shown in Figure 41 and described in Table 18.
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Figure 41. OSR_CFG Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
OSR[2:0] |
R-0b |
R/W-0b |
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Table 18. OSR_CFG Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-3 |
RESERVED |
R |
0b |
Reserved. Reads return 0. |
2-0 |
OSR[2:0] |
R/W |
0b |
Selects the oversampling ratio for ADC conversion result.
0b = No averaging
1b = 2 samples
10b = 4 samples
11b = 8 samples
100b = 16 samples
101b = 32 samples
110b = 64 samples
111b = 128 samples
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