JAJSGH2B November   2017  – September 2022 ADS7142-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Modes
    6. 6.6  Electrical Characteristics: Manual Mode
    7. 6.7  Electrical Characteristics: Autonomous Modes
    8. 6.8  Electrical Characteristics: High Precision Mode
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics: All Modes
    13. 6.13 Typical Characteristics: Manual Mode
    14. 6.14 Typical Characteristics: Autonomous Modes
    15. 6.15 Typical Characteristics: High-Precision Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
        1. 7.3.1.1 Two-Channel, Single-Ended Configuration
        2. 7.3.1.2 Single-Channel, Single-Ended Configuration With Remote Ground Sense
        3. 7.3.1.3 Single-Channel, Pseudo-Differential Configuration
      2. 7.3.2  Offset Calibration
      3. 7.3.3  Reference
      4. 7.3.4  ADC Transfer Function
      5. 7.3.5  Oscillator and Timing Control
      6. 7.3.6  I2C Address Selector
      7. 7.3.7  Data Buffer
        1. 7.3.7.1 Filling of the Data Buffer
        2. 7.3.7.2 Reading Data From the Data Buffer
      8. 7.3.8  Accumulator
      9. 7.3.9  Digital Window Comparator
      10. 7.3.10 I2C Protocol Features
        1. 7.3.10.1 General Call
        2. 7.3.10.2 General Call With Software Reset
        3. 7.3.10.3 General Call With Write Software Programmable Part of the Target Address
        4. 7.3.10.4 Configuring the ADC Into High-Speed I2C Mode
        5. 7.3.10.5 Bus Clear
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power Up and Reset
      2. 7.4.2 Manual Mode
        1. 7.4.2.1 Manual Mode With CH0 Only
        2. 7.4.2.2 Manual Mode With AUTO Sequence
      3. 7.4.3 Autonomous Modes
        1. 7.4.3.1 Autonomous Mode With Threshold Monitoring and Diagnostics
          1. 7.4.3.1.1 Autonomous Mode With Pre-ALERT Data
          2. 7.4.3.1.2 Autonomous Mode With Post-ALERT Data
        2. 7.4.3.2 Autonomous Mode With Burst Data
          1. 7.4.3.2.1 Autonomous Mode With Start Burst
          2. 7.4.3.2.2 Autonomous Mode With Stop Burst
      4. 7.4.4 High-Precision Mode
    5. 7.5 Programming
      1. 7.5.1 Reading Registers
        1. 7.5.1.1 Single Register Read
        2. 7.5.1.2 Reading a Continuous Block of Registers
      2. 7.5.2 Writing Registers
        1. 7.5.2.1 Single Register Write
        2. 7.5.2.2 Writing a Continuous Block of Registers
        3. 7.5.2.3 Set Bit
        4. 7.5.2.4 Clear Bit
    6. 7.6 Register Map
      1. 7.6.1 Page1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 ADS7142-Q1 as a Programmable Comparator With False Trigger Prevention and Diagnostics
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Programmable Thresholds and Hysteresis
          2. 8.2.1.2.2 False Trigger Prevention With an Event Counter
          3. 8.2.1.2.3 Fault Diagnostics With the Data Buffer
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Voltage and Temperature Monitoring in Remote Camera Modules Using the ADS7142-Q1
        1. 8.2.2.1 Design Requirements
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD and DVDD Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Electrostatic Discharge Caution
    2. 9.2 Glossary
    3. 9.3 Trademarks
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 サポート・リソース
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6.1 Page1 Registers

Table 7-5 lists the memory-mapped registers for the Page1 registers. All register offset addresses not listed in Table 7-5 should be considered as reserved locations and the register contents should not be modified.

Table 7-5 PAGE1 Registers
Address Acronym Register Name Section
0x0 OPMODE_I2CMODE_STATUS Device operation mode register #ADS7142-Q1_PAGE1_PAGE1_OPMODE_I2CMODE_STATUS
0x1 DATA_BUFFER_STATUS Data buffer status register #ADS7142-Q1_PAGE1_PAGE1_DATA_BUFFER_STATUS
0x2 ACCUMULATOR_STATUS Status of ADC accumulator #ADS7142-Q1_PAGE1_PAGE1_ACCUMULATOR_STATUS
0x3 ALERT_TRIG_CHID Alert trigeer channel ID #ADS7142-Q1_PAGE1_PAGE1_ALERT_TRIG_CHID
0x4 SEQUENCE_STATUS Sequence status register #ADS7142-Q1_PAGE1_PAGE1_SEQUENCE_STATUS
0x8 ACC_CH0_LSB CH0 accumulator data register (LSB) #ADS7142-Q1_PAGE1_PAGE1_ACC_CH0_LSB
0x9 ACC_CH0_MSB CH0 accumulated data register (MSB) #ADS7142-Q1_PAGE1_PAGE1_ACC_CH0_MSB
0xA ACC_CH1_LSB CH1 accumulated data register (LSB) #ADS7142-Q1_PAGE1_PAGE1_ACC_CH1_LSB
0xB ACC_CH1_MSB CH1 accumulated data register (MSB) #ADS7142-Q1_PAGE1_PAGE1_ACC_CH1_MSB
0xC ALERT_LOW_FLAGS Alert low flags register #ADS7142-Q1_PAGE1_PAGE1_ALERT_LOW_FLAGS
0xE ALERT_HIGH_FLAGS Alert high flags register #ADS7142-Q1_PAGE1_PAGE1_ALERT_HIGH_FLAGS
0x14 DEVICE_RESET Device reset register #ADS7142-Q1_PAGE1_PAGE1_DEVICE_RESET
0x15 OFFSET_CAL Offset calibration register #ADS7142-Q1_PAGE1_PAGE1_OFFSET_CAL
0x17 WKEY Write key for writing into DEVICE_RESET register #ADS7142-Q1_PAGE1_PAGE1_WKEY
0x18 OSC_SEL Oscillator selection register #ADS7142-Q1_PAGE1_PAGE1_OSC_SEL
0x19 NCLK_SEL nCLK selection register #ADS7142-Q1_PAGE1_PAGE1_NCLK_SEL
0x1C OPMODE_SEL Device operation mode selection #ADS7142-Q1_PAGE1_PAGE1_OPMODE_SEL
0x1E START_SEQUENCE Start channel scanning sequence register #ADS7142-Q1_PAGE1_PAGE1_START_SEQUENCE
0x1F ABORT_SEQUENCE Abort channel sequence register #ADS7142-Q1_PAGE1_PAGE1_ABORT_SEQUENCE
0x20 AUTO_SEQ_CHEN Auto sequencing channel select register #ADS7142-Q1_PAGE1_PAGE1_AUTO_SEQ_CHEN
0x24 CH_INPUT_CFG Channel input configuration register #ADS7142-Q1_PAGE1_PAGE1_CH_INPUT_CFG
0x28 DOUT_FORMAT_CFG Data buffer word configuration register #ADS7142-Q1_PAGE1_PAGE1_DOUT_FORMAT_CFG
0x2C DATA_BUFFER_OPMODE Data buffer operation mode register #ADS7142-Q1_PAGE1_PAGE1_DATA_BUFFER_OPMODE
0x30 ACC_EN Accumulator control register #ADS7142-Q1_PAGE1_PAGE1_ACC_EN
0x34 ALERT_CHEN Alert channel enable register #ADS7142-Q1_PAGE1_PAGE1_ALERT_CHEN
0x36 PRE_ALT_MAX_EVENT_COUNT Pre-alert count register #ADS7142-Q1_PAGE1_PAGE1_PRE_ALT_MAX_EVENT_COUNT
0x37 ALERT_DWC_EN Alert digital window comparator register #ADS7142-Q1_PAGE1_PAGE1_ALERT_DWC_EN
0x38 DWC_HTH_CH0_LSB CH0 high threshold LSB register #ADS7142-Q1_PAGE1_PAGE1_DWC_HTH_CH0_LSB
0x39 DWC_HTH_CH0_MSB CH0 high threshold MSB register #ADS7142-Q1_PAGE1_PAGE1_DWC_HTH_CH0_MSB
0x3A DWC_LTH_CH0_LSB CH0 low threshold LSB register #ADS7142-Q1_PAGE1_PAGE1___DWC_LTH_CH0_LSB
0x3B DWC_LTH_CH0_MSB CH0 low threshold MSB register #ADS7142-Q1_PAGE1_PAGE1_DWC_LTH_CH0_MSB
0x3C DWC_HTH_CH1_LSB CH1 high threshold LSB register #ADS7142-Q1_PAGE1_PAGE1_DWC_HTH_CH1_LSB
0x3D DWC_HTH_CH1_MSB CH1 high threshold MSB register #ADS7142-Q1_PAGE1_PAGE1_DWC_HTH_CH1_MSB
0x3E DWC_LTH_CH1_LSB CH1 low threshold LSB register #ADS7142-Q1_PAGE1_PAGE1_DWC_LTH_CH1_LSB
0x3F DWC_LTH_CH1_MSB CH1 low threshold MSB register #ADS7142-Q1_PAGE1_PAGE1_DWC_LTH_CH1_MSB
0x40 DWC_HYS_CH0 CH0 comparator hysterisis register #ADS7142-Q1_PAGE1_PAGE1_DWC_HYS_CH0
0x41 DWC_HYS_CH1 CH1 comparator hysterisis register #ADS7142-Q1_PAGE1_PAGE1_DWC_HYS_CH1

Complex bit access types are encoded to fit into small table cells. Table 7-6 shows the codes that are used for access types in this section.

Table 7-6 Page1 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y When this variable is used in a register name, an offset, or an address this variable refers to the value of a register array.

7.6.1.1 OPMODE_I2CMODE_STATUS Register (Address = 0x0) [Reset = 0x0]

OPMODE_I2CMODE_STATUS is shown in Figure 7-31 and described in Table 7-7.

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Device operation mode register

Figure 7-31 OPMODE_I2CMODE_STATUS Register
7 6 5 4 3 2 1 0
RESERVED HS_MODE DEV_OPMODE[1:0]
R-00000b R-0b R-00b
Table 7-7 OPMODE_I2CMODE_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 00000b Reserved bits. Read returns 00000b.
2 HS_MODE R 0b This bit indicates when device is in high speed mode for I2C Interface.
0b = Device is not in high speed mode for I2C Interface.
1b = Device is in high speed mode for I2C Interface.
1-0 DEV_OPMODE[1:0] R 00b These bits indicate funtional mode of the device.
00b = Device is operating in manual mode.
01b = Not used.
10b = Device is operating in autonomous monitoring mode.
11b = Device is operating in high precision mode.

7.6.1.2 DATA_BUFFER_STATUS Register (Address = 0x1) [Reset = 0x0]

DATA_BUFFER_STATUS is shown in Figure 7-32 and described in Table 7-8.

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Data buffer status register

Figure 7-32 DATA_BUFFER_STATUS Register
7 6 5 4 3 2 1 0
RESERVED DATA_WORDCOUNT[4:0]
R-000b R-00000b
Table 7-8 DATA_BUFFER_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 000b Reserved bits. Read returns 000b.
4-0 DATA_WORDCOUNT[4:0] R 00000b DATA_WORDCOUNT [00000] to [10000] = Number of entries filled in data buffer (0 to 16)

7.6.1.3 ACCUMULATOR_STATUS Register (Address = 0x2) [Reset = 0x0]

ACCUMULATOR_STATUS is shown in Figure 7-33 and described in Table 7-9.

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Status of ADC accumulator

Figure 7-33 ACCUMULATOR_STATUS Register
7 6 5 4 3 2 1 0
RESERVED ACC_COUNT[3:0]
R-0000b R-0000b
Table 7-9 ACCUMULATOR_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved bits. Read returns 0000b.
3-0 ACC_COUNT[3:0] R 0000b ACC_COUNT = Number of accumulation completed till last finished conversion.

7.6.1.4 ALERT_TRIG_CHID Register (Address = 0x3) [Reset = 0x0]

ALERT_TRIG_CHID is shown in Figure 7-34 and described in Table 7-10.

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Alert trigeer channel ID

Figure 7-34 ALERT_TRIG_CHID Register
7 6 5 4 3 2 1 0
ALERT_TRIG_CHID[3:0] RESERVED
R-0000b R-0000b
Table 7-10 ALERT_TRIG_CHID Register Field Descriptions
Bit Field Type Reset Description
7-4 ALERT_TRIG_CHID[3:0] R 0000b These bits provide the channel ID of channel which was first to set the alert output.
0000b = Channel 0.
0001b = Channel 1.
3-0 RESERVED R 0000b Reserved bits. Reads returns 0000b.

7.6.1.5 SEQUENCE_STATUS Register (Address = 0x4) [Reset = 0x0]

SEQUENCE_STATUS is shown in Figure 7-35 and described in Table 7-11.

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Sequence status register

Figure 7-35 SEQUENCE_STATUS Register
7 6 5 4 3 2 1 0
RESERVED SEQ_ERR_ST[1:0] RESERVED
R-00000b R-00b R-0b
Table 7-11 SEQUENCE_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 00000b Reserved bits. Read returns 00000b.
2-1 SEQ_ERR_ST[1:0] R 00b These bits give status of device sequence.
00b = Auto sequencing disabled, no error.
01b = Auto sequencing enabled, no error.
10b = Not used.
11b = Auto sequencing enabled, device in error.
0 RESERVED R 0b Reserved bit. Read returns 0b.

7.6.1.6 ACC_CH0_LSB Register (Address = 0x8) [Reset = 0x0]

ACC_CH0_LSB is shown in Figure 7-36 and described in Table 7-12.

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CH0 accumulator data register (LSB)

Figure 7-36 ACC_CH0_LSB Register
7 6 5 4 3 2 1 0
CH0_LSB[7:0]
R-00000000b
Table 7-12 ACC_CH0_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 CH0_LSB[7:0] R 00000000b LSB of accumulated data for CH0.

7.6.1.7 ACC_CH0_MSB Register (Address = 0x9) [Reset = 0x0]

ACC_CH0_MSB is shown in Figure 7-37 and described in Table 7-13.

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CH0 accumulated data register (MSB)

Figure 7-37 ACC_CH0_MSB Register
7 6 5 4 3 2 1 0
CH0_MSB[7:0]
R-00000000b
Table 7-13 ACC_CH0_MSB Register Field Descriptions
Bit Field Type Reset Description
7-0 CH0_MSB[7:0] R 00000000b MSB of accumulated data for CH0.

7.6.1.8 ACC_CH1_LSB Register (Address = 0xA) [Reset = 0x0]

ACC_CH1_LSB is shown in Figure 7-38 and described in Table 7-14.

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CH1 accumulated data register (LSB)

Figure 7-38 ACC_CH1_LSB Register
7 6 5 4 3 2 1 0
CH1_LSB[7:0]
R-00000000b
Table 7-14 ACC_CH1_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 CH1_LSB[7:0] R 00000000b LSB of accumulated data for CH1.

7.6.1.9 ACC_CH1_MSB Register (Address = 0xB) [Reset = 0x0]

ACC_CH1_MSB is shown in Figure 7-39 and described in Table 7-15.

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CH1 accumulated data register (MSB)

Figure 7-39 ACC_CH1_MSB Register
7 6 5 4 3 2 1 0
CH1_MSB[7:0]
R-00000000b
Table 7-15 ACC_CH1_MSB Register Field Descriptions
Bit Field Type Reset Description
7-0 CH1_MSB[7:0] R 00000000b MSB of accumulated data for CH1.

7.6.1.10 ALERT_LOW_FLAGS Register (Address = 0xC) [Reset = 0x0]

ALERT_LOW_FLAGS is shown in Figure 7-40 and described in Table 7-16.

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Alert low flags register

Figure 7-40 ALERT_LOW_FLAGS Register
7 6 5 4 3 2 1 0
RESERVED ALERT_LOW_CH1 ALERT_LOW_CH0
R-000000b R/W-0b R/W-0b
Table 7-16 ALERT_LOW_FLAGS Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 000000b Reserved bits. Read returns 000000b.
1 ALERT_LOW_CH1 R/W 0b This bit indicates alert on low side comparator for CH1.
0b = Alert is not set for low side comparator for CH1.
1b = Alert is set for low side comparator for CH1.
0 ALERT_LOW_CH0 R/W 0b This bit indicates alert on low side comparator for CH0.
0b = Alert is not set for low side comparator for CH0.
1b = Alert is set for low side comparator for CH0.

7.6.1.11 ALERT_HIGH_FLAGS Register (Address = 0xE) [Reset = 0x0]

ALERT_HIGH_FLAGS is shown in Figure 7-41 and described in Table 7-17.

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Alert high flags register

Figure 7-41 ALERT_HIGH_FLAGS Register
7 6 5 4 3 2 1 0
RESERVED ALERT_HIGH_CH1 ALERT_HIGH_CH0
R-000000b R/W-0b R/W-0b
Table 7-17 ALERT_HIGH_FLAGS Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 000000b Reserved bits. Read returns 000000b.
1 ALERT_HIGH_CH1 R/W 0b This bit indicates alert on high side comparator of CH1.
0b = Alert is not set for high side comparator for CH1.
1b = Alert is set for high side comparator for CH1.
0 ALERT_HIGH_CH0 R/W 0b This bit indicates alert on high side comparator for CH0.
0b = Alert is not set for high side comparator for CH0.
1b = Alert is set for high side comparator for CH0.

7.6.1.12 DEVICE_RESET Register (Address = 0x14) [Reset = 0x0]

DEVICE_RESET is shown in Figure 7-42 and described in Table 7-18.

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Device reset register

Figure 7-42 DEVICE_RESET Register
7 6 5 4 3 2 1 0
RESERVED DEV_RST
R-0000000b W-0b
Table 7-18 DEVICE_RESET Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R 0000000b Reserved bits. Read returns 0000000b.
0 DEV_RST W 0b Writing 1 to this bit resets the device.

7.6.1.13 OFFSET_CAL Register (Address = 0x15) [Reset = 0x0]

OFFSET_CAL is shown in Figure 7-43 and described in Table 7-19.

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Offset calibration register

Figure 7-43 OFFSET_CAL Register
7 6 5 4 3 2 1 0
RESERVED TRIG_OFFCAL
R-0000000b W-0b
Table 7-19 OFFSET_CAL Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R 0000000b Reserved bits. Read returns 0000000b.
0 TRIG_OFFCAL W 0b Writing 1 into this bit triggers internal offset calibration.

7.6.1.14 WKEY Register (Address = 0x17) [Reset = 0x0]

WKEY is shown in Figure 7-44 and described in Table 7-20.

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Write key for writing into DEVICE_RESET register

Figure 7-44 WKEY Register
7 6 5 4 3 2 1 0
RESERVED WKEY[3:0]
R-0000b R/W-0000b
Table 7-20 WKEY Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved bits. Do not write. Read returns 0000b.
3-0 WKEY[3:0] R/W 0000b Write 1010b into these bits to get write access for the DEVICE_RESET register. WKEY register is not reset to default value on device reset (see Reset section). After coming out of device reset, write 00h to the WKEY register to prevent erroneous reset.

7.6.1.15 OSC_SEL Register (Address = 0x18) [Reset = 0x0]

OSC_SEL is shown in Figure 7-45 and described in Table 7-21.

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Oscillator selection register

Figure 7-45 OSC_SEL Register
7 6 5 4 3 2 1 0
RESERVED HSZ_LP
R-0000000b R/W-0b
Table 7-21 OSC_SEL Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R 0000000b Reserved bits. Read returns 0000000b.
0 HSZ_LP R/W 0b This bit selects oscillator used for the conversion process and cycle time for a single conversion.
0b = Device uses high speed oscillator.
1b = Device uses low power oscillator.

7.6.1.16 NCLK_SEL Register (Address = 0x19) [Reset = 0x0]

NCLK_SEL is shown in Figure 7-46 and described in Table 7-22.

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nCLK selection register

Figure 7-46 NCLK_SEL Register
7 6 5 4 3 2 1 0
NCLK[7:0]
R/W-00000000b
Table 7-22 NCLK_SEL Register Field Descriptions
Bit Field Type Reset Description
7-0 NCLK[7:0] R/W 00000000b Sets number of clocks of the oscillator that the device uses for one conversion cycle. When using the High Speed Oscillator: For Value x written into the nCLK register • if x ≤ 21, nCLK is set to 21 (00010101b) • if x > 21, nCLK is set to x When using the Low Power Oscillator, For Value x written into the nCLK register: • if x ≤ 18, nCLK is set to 18 (00010010b) • if x > 18, nCLK is set to x

7.6.1.17 OPMODE_SEL Register (Address = 0x1C) [Reset = 0x0]

OPMODE_SEL is shown in Figure 7-47 and described in Table 7-23.

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Device operation mode selection

Figure 7-47 OPMODE_SEL Register
7 6 5 4 3 2 1 0
RESERVED SEL_OPMODE[2:0]
R-00000b R/W-000b
Table 7-23 OPMODE_SEL Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 00000b Reserved bits. Read returns 00000b
2-0 SEL_OPMODE[2:0] R/W 000b These bits set the functional mode for the device.
000b = Manual mode with CH0 only (Default mode).
001b = Manual mode with CH0 only (Default mode).
010b = Reserved. Do not use.
011b = Reserved. Do not use.
100b = Manual mode with AUTO Sequencing enabled.
101b = Manual Mode with AUTO Sequencing enabled.
110b = Autonomous monitoring mode with AUTO sequencing enabled.
111b = High precision mode with AUTO sequencing enabled.

7.6.1.18 START_SEQUENCE Register (Address = 0x1E) [Reset = 0x0]

START_SEQUENCE is shown in Figure 7-48 and described in Table 7-24.

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Start channel scanning sequence register

Figure 7-48 START_SEQUENCE Register
7 6 5 4 3 2 1 0
RESERVED SEQ_START
R-0000000b W-0b
Table 7-24 START_SEQUENCE Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R 0000000b Reserved bits. Read returns 0000000b.
0 SEQ_START W 0b Setting this bit to 1 brings the BUSY/RDY pin high and starts the first conversion in the sequence.

7.6.1.19 ABORT_SEQUENCE Register (Address = 0x1F) [Reset = 0x0]

ABORT_SEQUENCE is shown in Figure 7-49 and described in Table 7-25.

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Abort channel sequence register

Figure 7-49 ABORT_SEQUENCE Register
7 6 5 4 3 2 1 0
RESERVED SEQ_ABORT
R-0000000b W-0b
Table 7-25 ABORT_SEQUENCE Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R 0000000b Reserved bits. Read returns 0000000b.
0 SEQ_ABORT W 0b Setting this bit to 1 aborts the ongoing conversion and brings the BUSY/RDY pin low.

7.6.1.20 AUTO_SEQ_CHEN Register (Address = 0x20) [Reset = 0x3]

AUTO_SEQ_CHEN is shown in Figure 7-50 and described in Table 7-26.

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Auto sequencing channel select register

Figure 7-50 AUTO_SEQ_CHEN Register
7 6 5 4 3 2 1 0
RESERVED AUTOSEQ_EN_CH1 AUTOSEQ_EN_CH0
R-000000b R/W-1b R/W-1b
Table 7-26 AUTO_SEQ_CHEN Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 000000b Reserved bits. Read returns 000000b.
1 AUTOSEQ_EN_CH1 R/W 1b This bit selects CH1 for auto sequencing.
0b = Channel 1 is not selected for auto sequencing.
1b = Channel 1 is selected for auto sequencing.
0 AUTOSEQ_EN_CH0 R/W 1b This bit selects CH0 for auto sequencing.
0b = Channel 0 is not selected for auto sequencing.
1b = Channel 0 is selected for auto sequencing.

7.6.1.21 CH_INPUT_CFG Register (Address = 0x24) [Reset = 0x0]

CH_INPUT_CFG is shown in Figure 7-51 and described in Table 7-27.

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Channel input configuration register

Figure 7-51 CH_INPUT_CFG Register
7 6 5 4 3 2 1 0
RESERVED CH0_CH1_IP_CFG[1:0]
R-000000b R/W-00b
Table 7-27 CH_INPUT_CFG Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 000000b Reserved bits. Read returns 000000b.
1-0 CH0_CH1_IP_CFG[1:0] R/W 00b This bit selects configuration for the input pins.
00b = Two-channel, single-ended configuration.
01b = Single-channel, single-ended configuration with remote ground sensing.
10b = Single-channel, pseudo-differential configuration.
11b = Two-channel, single-ended configuration.

7.6.1.22 DOUT_FORMAT_CFG Register (Address = 0x28) [Reset = 0x0]

DOUT_FORMAT_CFG is shown in Figure 7-52 and described in Table 7-28.

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Data buffer word configuration register

Figure 7-52 DOUT_FORMAT_CFG Register
7 6 5 4 3 2 1 0
RESERVED DOUT_FORMAT[1:0]
R-000000b R/W-00b
Table 7-28 DOUT_FORMAT_CFG Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 000000b Reserved bits. Read returns 000000b.
1-0 DOUT_FORMAT[1:0] R/W 00b These bits select 16-bit content of the data word in the data buffer.
00b = 12-bit conversion result followed by 0000b.
01b = 12-bit conversion result followed by 3-bit channel ID (000b for CH0, 001b for CH1).
10b = 12-bit conversion result followed by 3-bit channel ID (000b for CH0, 001b for CH1) followed by DATA_VALID bit.
11b = 12-bit conversion result followed by 0000b.

7.6.1.23 DATA_BUFFER_OPMODE Register (Address = 0x2C) [Reset = 0x1]

DATA_BUFFER_OPMODE is shown in Figure 7-53 and described in Table 7-29.

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Data buffer operation mode register

Figure 7-53 DATA_BUFFER_OPMODE Register
7 6 5 4 3 2 1 0
RESERVED STARTSTOP_CNTRL[2:0]
R-00000b R/W-001b
Table 7-29 DATA_BUFFER_OPMODE Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 00000b Reserved bits. Read returns 00000b.
2-0 STARTSTOP_CNTRL[2:0] R/W 001b These bits select data buffer mode of operation.
000b = Stop burst mode.
001b = Start burst mode, default.
010b = Reserved, do not use.
011b = Reserved, do not use.
100b = Pre alert data mode.
101b = Reserved, do not use.
110b = Post alert data mode.
111b = Reserved, do not use.

7.6.1.24 ACC_EN Register (Address = 0x30) [Reset = 0x0]

ACC_EN is shown in Figure 7-54 and described in Table 7-30.

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Accumulator control register

Figure 7-54 ACC_EN Register
7 6 5 4 3 2 1 0
RESERVED EN_ACC[3:0]
R-0000b R/W-0000b
Table 7-30 ACC_EN Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved bits. Read returns 0000b.
3-0 EN_ACC[3:0] R/W 0000b These bits enable accumulator function of device. 0001b to 1110b settings are reserved. Do not use.
0000b = Accumulator is disabled.
1111b = Accumulator is enabled.

7.6.1.25 ALERT_CHEN Register (Address = 0x34) [Reset = 0x0]

ALERT_CHEN is shown in Figure 7-55 and described in Table 7-31.

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Alert channel enable register

Figure 7-55 ALERT_CHEN Register
7 6 5 4 3 2 1 0
RESERVED ALERT_EN_CH1 ALERT_EN_CH0
R-000000b R/W-0b R/W-0b
Table 7-31 ALERT_CHEN Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 000000b Reserved bits. Read returns 000000b.
1 ALERT_EN_CH1 R/W 0b This bit enables alert functionality of CH1.
0b = Alert is disabled for CH1, default.
1b = Alert is enabled for CH1.
0 ALERT_EN_CH0 R/W 0b This bit enables alert functionality for CH0.
0b = Alert is disabled for CH0, default.
1b = Alert is enabled for CH0.

7.6.1.26 PRE_ALT_MAX_EVENT_COUNT Register (Address = 0x36) [Reset = 0x0]

PRE_ALT_MAX_EVENT_COUNT is shown in Figure 7-56 and described in Table 7-32.

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Pre-alert count register

Figure 7-56 PRE_ALT_MAX_EVENT_COUNT Register
7 6 5 4 3 2 1 0
PREALERT_COUNT[3:0] RESERVED
R/W-0000b R-0000b
Table 7-32 PRE_ALT_MAX_EVENT_COUNT Register Field Descriptions
Bit Field Type Reset Description
7-4 PREALERT_COUNT[3:0] R/W 0000b These bits set the Pre-Alert Event Count = PREALERT_COUNT [7:4] + 1
3-0 RESERVED R 0000b Reserved bits. Read returns 0000b.

7.6.1.27 ALERT_DWC_EN Register (Address = 0x37) [Reset = 0x0]

ALERT_DWC_EN is shown in Figure 7-57 and described in Table 7-33.

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Alert digital window comparator register

Figure 7-57 ALERT_DWC_EN Register
7 6 5 4 3 2 1 0
RESERVED DWC_BLOCK_EN
R-0000000b R/W-0b
Table 7-33 ALERT_DWC_EN Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R 0000000b Reserved bits. Read returns 0000000b.
0 DWC_BLOCK_EN R/W 0b This bit enables digital window comparator block.
0b = Disables digital window comparator.
1b = Enables digital window comparator.

7.6.1.28 DWC_HTH_CH0_LSB Register (Address = 0x38) [Reset = 0x0]

DWC_HTH_CH0_LSB is shown in Figure 7-58 and described in Table 7-34.

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CH0 high threshold LSB register

Figure 7-58 DWC_HTH_CH0_LSB Register
7 6 5 4 3 2 1 0
HTH_CH0_LSB[7:0]
R/W-00000000b
Table 7-34 DWC_HTH_CH0_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 HTH_CH0_LSB[7:0] R/W 00000000b These are 8 least significant bits of high threshold for CH0.

7.6.1.29 DWC_HTH_CH0_MSB Register (Address = 0x39) [Reset = 0x0]

DWC_HTH_CH0_MSB is shown in Figure 7-59 and described in Table 7-35.

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CH0 high threshold MSB register

Figure 7-59 DWC_HTH_CH0_MSB Register
7 6 5 4 3 2 1 0
RESERVED HTH_CH0_MSB[3:0]
R-0000b R/W-0000b
Table 7-35 DWC_HTH_CH0_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved bits. Read returns 0000b.
3-0 HTH_CH0_MSB[3:0] R/W 0000b These are 4 most significant bits of high threshold for CH0.

7.6.1.30 DWC_LTH_CH0_LSB Register (Address = 0x3A) [Reset = 0x0]

DWC_LTH_CH0_LSB is shown in Figure 7-60 and described in Table 7-36.

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CH0 low threshold LSB register

Figure 7-60 DWC_LTH_CH0_LSB Register
7 6 5 4 3 2 1 0
LTH_CH0_LSB[7:0]
R/W-00000000b
Table 7-36 DWC_LTH_CH0_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 LTH_CH0_LSB[7:0] R/W 00000000b These are 8 least significant bits of low threshold for CH0.

7.6.1.31 DWC_LTH_CH0_MSB Register (Address = 0x3B) [Reset = 0x0]

DWC_LTH_CH0_MSB is shown in Figure 7-61 and described in Table 7-37.

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CH0 low threshold MSB register

Figure 7-61 DWC_LTH_CH0_MSB Register
7 6 5 4 3 2 1 0
RESERVED LTH_CH0_MSB[3:0]
R-0000b R/W-0000b
Table 7-37 DWC_LTH_CH0_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved bits. Read returns 0000b.
3-0 LTH_CH0_MSB[3:0] R/W 0000b These are 4 most significant bits of low threshold for CH0.

7.6.1.32 DWC_HTH_CH1_LSB Register (Address = 0x3C) [Reset = 0x0]

DWC_HTH_CH1_LSB is shown in Figure 7-62 and described in Table 7-38.

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CH1 high threshold LSB register

Figure 7-62 DWC_HTH_CH1_LSB Register
7 6 5 4 3 2 1 0
HTH_CH1_LSB[7:0]
R/W-00000000b
Table 7-38 DWC_HTH_CH1_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 HTH_CH1_LSB[7:0] R/W 00000000b These are 8 least significant bits of high threshold for CH1.

7.6.1.33 DWC_HTH_CH1_MSB Register (Address = 0x3D) [Reset = 0x0]

DWC_HTH_CH1_MSB is shown in Figure 7-63 and described in Table 7-39.

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CH1 high threshold MSB register

Figure 7-63 DWC_HTH_CH1_MSB Register
7 6 5 4 3 2 1 0
RESERVED HTH_CH1_MSB[3:0]
R-0000b R/W-0000b
Table 7-39 DWC_HTH_CH1_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved bits. Read returns 0000b.
3-0 HTH_CH1_MSB[3:0] R/W 0000b These are 4 most significant bits of high threshold for CH1.

7.6.1.34 DWC_LTH_CH1_LSB Register (Address = 0x3E) [Reset = 0x0]

DWC_LTH_CH1_LSB is shown in Figure 7-64 and described in Table 7-40.

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CH1 low threshold LSB register

Figure 7-64 DWC_LTH_CH1_LSB Register
7 6 5 4 3 2 1 0
LTH_CH1_LSB[7:0]
R/W-00000000b
Table 7-40 DWC_LTH_CH1_LSB Register Field Descriptions
Bit Field Type Reset Description
7-0 LTH_CH1_LSB[7:0] R/W 00000000b These are 8 least significant bits of low threshold for CH1.

7.6.1.35 DWC_LTH_CH1_MSB Register (Address = 0x3F) [Reset = 0x0]

DWC_LTH_CH1_MSB is shown in Figure 7-65 and described in Table 7-41.

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CH1 low threshold MSB register

Figure 7-65 DWC_LTH_CH1_MSB Register
7 6 5 4 3 2 1 0
RESERVED LTH_CH1_MSB[3:0]
R-0000b R/W-0000b
Table 7-41 DWC_LTH_CH1_MSB Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved bits. Read returns 0000b.
3-0 LTH_CH1_MSB[3:0] R/W 0000b These are 4 most significant bits of low threshold for CH1.

7.6.1.36 DWC_HYS_CH0 Register (Address = 0x40) [Reset = 0x0]

DWC_HYS_CH0 is shown in Figure 7-66 and described in Table 7-42.

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CH0 comparator hysterisis register

Figure 7-66 DWC_HYS_CH0 Register
7 6 5 4 3 2 1 0
RESERVED HYS_CH0[5:0]
R-00b R/W-000000b
Table 7-42 DWC_HYS_CH0 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b Reserved bits. Read returns 00b.
5-0 HYS_CH0[5:0] R/W 000000b These bits set hysteresis for both comparators for CH0.

7.6.1.37 DWC_HYS_CH1 Register (Address = 0x41) [Reset = 0x0]

DWC_HYS_CH1 is shown in Figure 7-67 and described in Table 7-43.

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CH1 comparator hysterisis register

Figure 7-67 DWC_HYS_CH1 Register
7 6 5 4 3 2 1 0
RESERVED HYS_CH1[5:0]
R-00b R/W-000000b
Table 7-43 DWC_HYS_CH1 Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 00b Reserved bits. Read returns 00b.
5-0 HYS_CH1[5:0] R/W 000000b These bits set hysteresis for both comparators for CH1.